Title:
MEMORY TEST SET
Document Type and Number:
WIPO Patent Application WO/1998/027556
Kind Code:
A1
Abstract:
A set for testing memories of both parallel input/parallel output type and serial input/serial output type which, when used for testing a serial input/serial output type memory, divides fail data contained in serially outputted read-out data bit by bit and stores the same in a failure analysis memory at the different points of time on the time-axis so that the position of a defective bit can be specified. The test set is provided with a fail multiplexer (14) which selectively fetches outputs from the terminal of a memory (10) under test on the output side of a logic comparator (13) and with a bit selector (17) between the multiplexer (14) and a failure analysis memory (15). At the time of testing the memory of serial input/serial output type, the selector (17) divides the serial fail data outputted from the multiplexer (14) bit by bit and gives the data to the memory (15) at the different points of time on the time-axis, thus storing the position of the defective bit in the memory (15).
Inventors:
GOISHI MASARU (JP)
Application Number:
PCT/JP1997/004720
Publication Date:
June 25, 1998
Filing Date:
December 19, 1997
Export Citation:
Assignee:
ADVANTEST CORP (JP)
GOISHI MASARU (JP)
GOISHI MASARU (JP)
International Classes:
G01R31/3193; G11C29/00; G01R31/28; G11C29/56; G11C29/44; (IPC1-7): G11C29/00; G01R31/28
Foreign References:
| JPH06148278A | 1994-05-27 | |||
| JPH03102274A | 1991-04-26 | |||
| JPH0238979A | 1990-02-08 | |||
| JPS5673354A | 1981-06-18 |
Attorney, Agent or Firm:
Kusano, Takashi (2-21 Shinjuku 4-chom, Shinjuku-ku Tokyo 160, JP)
Download PDF: