TECHNICAL FIELD

Embodiments of the disclosure are in the field of semiconductor structures and processing and, in particular, metal spacer-based approaches for conductive interconnect and via fabrication, and the resulting structures.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.

Integrated circuits commonly include electrically conductive microelectronic structures, which are known in the art as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are typically formed by a lithographic process. Representatively, a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed in order to form an opening in the photoresist layer. Next, an opening for the via may be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1A illustrates a cross-sectional view of interconnect lines of a metallization layer. Figure IB illustrates a cross-sectional view of interconnect lines of a metallization layer, in accordance with an embodiment of the present disclosure.

Figures 2A-20 illustrate cross-sectional views of portions of integrated circuit layers representing various operations in a method involving metal spacer and self-aligned conductive via formation for back end of line (BEOL) interconnect fabrication, in accordance with an embodiment of the present disclosure. Figure 3 illustrates a plan view of a portion of an integrated circuit layer representing an operation in a method involving metal spacer and self-aligned conductive via formation for back end of line (BEOL) interconnect fabrication, in accordance with an embodiment of the present disclosure.

Figure 4A illustrates a cross-sectional view of a portion of an integrated circuit layer representing an operation in another method involving metal spacer formation for back end of line (BEOL) interconnect fabrication, in accordance with another embodiment of the present disclosure.

Figure 4B illustrates a cross-sectional view of a portion of an integrated circuit layer representing an operation in another method involving metal spacer formation for back end of line (BEOL) interconnect fabrication, in accordance with another embodiment of the present disclosure.

Figure 5 A illustrates a cross-sectional view of a starting structure following deposition, but prior to patterning, of a hardmask material layer formed on an interlayer dielectric (ILD) layer, in accordance with an embodiment of the present disclosure.

Figure 5B illustrates a cross-sectional view of the structure of Figure 5 A following patterning of the hardmask layer by pitch halving, in accordance with an embodiment of the present disclosure.

Figure 6 illustrates cross- sectional views in a spacer-based-sextuple-patterning (SBSP) processing scheme which involves pitch division by a factor of six, in accordance with an embodiment of the present disclosure.

Figure 7A illustrates a cross-sectional view of a non-planar semiconductor device having a self-aligned gate contact, in accordance with an embodiment of the present disclosure.

Figure 7B illustrates a plan view taken along the a-a' axis of the semiconductor device of Figure 7A, in accordance with an embodiment of the present disclosure.

Figure 8 illustrates a computing device in accordance with one implementation of an embodiment of the present disclosure.

Figure 9 is an interposer implementing one or more embodiments of the disclosure. DESCRIPTION OF THE EMBODIMENTS

In the past, the sizes and the spacing of vias has progressively decreased, and it is expected that in the future the sizes and the spacing of the vias will continue to progressively decrease, for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.). One measure of the size of the vias is the critical dimension of the via opening. One measure of the spacing of the vias is the via pitch. Via pitch represents the center-to-center distance between the closest adjacent vias.

When patterning extremely small vias with extremely small pitches by such lithographic processes, several challenges present themselves, especially when the pitches are around 70 - 90 nanometers (nm) or less and/or when the critical dimensions of the via openings are around 35nm or less. One such challenge is that the overlay between the vias and the overlying interconnects, and the overlay between the vias and the underlying landing interconnects, generally need to be controlled to high tolerances on the order of a quarter of the via pitch. As via pitches scale ever smaller over time, the overlay tolerances tend to scale with them at an even greater rate than lithographic equipment is able to keep up.

Another such challenge is that the critical dimensions of the via openings generally tend to scale faster than the resolution capabilities of the lithographic scanners. Shrink technologies exist to shrink the critical dimensions of the via openings. However, the shrink amount tends to be limited by the minimum via pitch, as well as by the ability of the shrink process to be sufficiently optical proximity correction (OPC) neutral, and to not significantly compromise line width roughness (LWR) and/or critical dimension uniformity (CDU).

Yet another such challenge is that the LWR and/or CDU characteristics of photoresists generally need to improve as the critical dimensions of the via openings decrease in order to maintain the same overall fraction of the critical dimension budget. However, currently the LWR and/or CDU characteristics of most photoresists are not improving as rapidly as the critical dimensions of the via openings are decreasing.

A further such challenge is that the extremely small via pitches generally tend to be below the resolution capabilities of even extreme ultraviolet (EUV) lithographic scanners. As a result, commonly several different lithographic masks may be used, which tend to increase the costs. At some point, if pitches continue to decrease, it may not be possible, even with multiple masks, to print via openings for these extremely small pitches using EUV scanners.

Thus, improvements are needed in the area of back end metallization manufacturing technologies for fabricating metal vias.

Metal spacer-based approaches for conductive interconnect and via fabrication, and the resulting structures, are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure.

Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Embodiments described herein may be directed to back end of line (BEOL)

semiconductor processing and structures. BEOL is the second portion of IC fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

Embodiments described herein may be directed to front-end-of-line (FEOL)

semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described below may be applicable to BEOL processing and structures, FEOL processing and structures, or both BEOL and FEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing.

One or more embodiments described herein are directed to subtractive metal spacers with hardmasks thereon for improving self-alignment. Embodiments may include one or more of angled etching, metal spacer formation, or spacer-based patterning. One or more embodiments involve the use of metal spacers as interconnects to enable high conductivity interconnects at tight pitch, without sacrificing alignment capabilities at lithography.

One or more embodiments described herein involve the use of iterative spacer or thin film deposition to define all or substantially all of the final critical small features for a layer such as a BEOL layer. The variation of such features may be better than +/- lnm. Multiple materials may be employed to enable "coloring" of patterns to enable addressing alternative features (e.g., vias, plugs, etc.) with enlarged margin for edge placement errors. Embodiments may be implemented to provide improved via shorting margin by self-alignment with hardmask "coloring", e.g., for the lOnm and smaller technology nodes. Integration of such "color" materials, which may be alternating hardmask materials of differing composition and/or etch selectivity, are used to enable such self-alignment.

To provide context, current solutions to improve shorting margin may include: (1) using metal recess to fill alternate metal trenches with different hard masks, or (2) recessing the metal or ILD to "steer" the via towards the line of interest. To provide further context, local interconnect and tight-pitch metal layers may require the use of self-aligned vias.

In accordance with one or more embodiments of the present disclosure, angled spacer etching is used to construct alternating hardmasks on top of subtractively-patterned metal spacers for interconnects. Such an approach may be implemented to enable adding plugs or vias to one set of metal interconnect without affecting an adjacent trench. In accordance with one or more embodiments, such an approach may be applied to any interconnect metal layer in the BEOL and, possibly, to gate contacts, examples of which are described below.

In one particular aspect, one or more embodiments are directed to an approach for fabricating metal lines as well as associated conductive vias. Conductive vias or vias, by definition, are used to land on a previous layer metal pattern. In this vein, embodiments described herein enable a more robust interconnect fabrication scheme since constraints on lithography equipment is relaxed. Such an interconnect fabrication scheme can be used to save numerous alignment/exposures, and can be used to reduce total process operations and processing time otherwise required for patterning such features using conventional approaches. Other benefits may include improvements in yield, or the prevention of shorting to a wrong line.

As an example of a conventional structure, Figure 1 A illustrates a cross-sectional view of interconnect lines of a metallization layer. Referring to Figure 1 A, a substrate 102 has an etch- stop layer 104 thereon or there above. An inter-layer dielectric (ILD) material 106 is on the etch- stop layer 104. A plurality of metal interconnect lines 108 is in the ILD material 106. Top surfaces of the plurality of metal interconnect lines 108 are exposed and are co-planar with the ILD material 106.

As an example of a target structure, Figure IB illustrates a cross-sectional view of interconnect lines of a metallization layer, in accordance with an embodiment of the present disclosure. Referring to Figure IB, a substrate 152 has an etch-stop layer 154 thereon or there above. An inter-layer dielectric (ILD) material 156 is on the etch-stop layer 154. A plurality of metal interconnect lines 158 is in the ILD material 156. Top surfaces of the plurality of metal interconnect lines 158 are recessed below the top of the ILD material 156 and are covered with alternating first hardmask components 160 and second hardmask components 162. In an embodiment, the alternating first hardmask components 160 and second hardmask components 162 have different etch selectivity and are referred to as "colored" hardmasks since they can be etched relative to one another.

In an exemplary approach using different "color" hardmask materials as a foundation for self-aligned via fabrication, Figures 2A-20 illustrate cross-sectional views of portions of integrated circuit layers representing various operations in a method involving metal spacer and self-aligned conductive via formation for back end of line (BEOL) interconnect fabrication, in accordance with an embodiment of the present disclosure.

Referring to Figure 2A, a method of fabricating a back end of line (BEOL) metallization layer includes forming a dielectric backbone grating 206 on an etch-stop layer 204 above a substrate 202 to provide a starting structure 200. The etch-stop layer 204 may be on the substrate 200 or may be on another metallization layer 203, as is depicted in Figure 2A. In an

embodiment, the dielectric backbone grating 206 is formed using a pitch division patterning process flow. Non-limiting examples of such pitch division schemes are described in greater detail below in association with Figures 5A, 5B and 6. It is to be appreciated that the fabrication of dielectric backbone grating 206 may first involve pitch division, or may not. In either case, but particularly when pitch division is also used, embodiments may enable continued scaling of the pitch of metal layers beyond the resolution capability of state-of-the art lithography equipment.

Referring to Figure 2B, a conformal conductive layer 208 is formed over the dielectric backbone grating 208.

Referring to Figure 2C, conductive spacers 210 are formed from the conformal conductive layer 208. The conductive spacers 210 are along sidewalls of the dielectric backbone grating 206.

Referring to Figure 2D, the conductive spacers 210 are recessed relative to the dielectric backbone grating 206 to form conductive lines 212 along the sidewalls of the dielectric backbone grating 206.

Referring to Figure 2E, a lower dielectric material 214 is formed on the etch-stop layer 204 between the conductive lines 212. In an embodiment, the lower dielectric material 214 is a reflowable oxide material. In an embodiment, the lower dielectric material 214 is composed of a same dielectric material as the dielectric backbone grating 206. In another embodiment, the lower dielectric material 214 is composed of a different dielectric material than the dielectric backbone grating 206.

Referring to Figure 2F, a first conformal dielectric layer 216 is formed over the dielectric backbone grating 206, over the conductive lines 212, and over the lower dielectric material 214.

Referring to Figure 2G, first dielectric spacers 218 are formed from the first conformal dielectric layer 216. The first dielectric spacers 218 aligned with the conductive lines 212. In an embodiment, the first dielectric spacers 218 are formed from the first conformal dielectric layer 216 using an anisotropic etch process.

Referring to Figure 2H, individual ones of the first dielectric spacers 218 are removed from a second side of the dielectric backbone grating 206 and individual ones of the first dielectric spacers 218 are left on a first side of the dielectric backbone grating 206 opposite the second side to provide a first hardmask component 222 over first of alternating ones of the conductive lines 212. In an embodiment, individual ones of the first dielectric spacers 218 are removed from the second side of the dielectric backbone grating 206 by using an angled etch process 220 directed at the second side of the dielectric backbone grating 206.

Referring to Figure 21, a second conformal dielectric layer 224 is formed over the dielectric backbone grating 206, over the first hardmask component 222, over the conductive lines 212, and over the lower dielectric material 214.

Referring to Figure 2J, second dielectric spacers 227/226 are formed from the second conformal dielectric layer 224. In an embodiment, the second dielectric spacers 227/226 are formed from the second conformal dielectric layer 224 using an anisotropic etch process.

Referring to Figure 2K, individual ones 227 of the second dielectric spacers 227/226 are removed from the first side of the dielectric backbone grating 206. Individual ones 226 of the second dielectric spacers 227/226 remain on the second side of the dielectric backbone grating 206 opposite the first side to provide a second hardmask component 226 over and aligned with second of alternating ones of the conductive lines 212. In an embodiment, the individual ones 227 of the second dielectric spacers 227/226 are removed from the first side of the dielectric backbone grating 206 includes using an angled etch process 228 directed at the first side of the dielectric backbone grating 206.

Referring to Figure 2L, an upper dielectric material 230 is formed on the lower dielectric material 214 between the first hardmask component 222 and the second hardmask component 226. In an embodiment, the upper dielectric material 230 is a reflowable oxide material. In an embodiment, the upper dielectric material 230 is composed of a same dielectric material as the dielectric backbone grating 206. In another embodiment, the upper dielectric material 230 is composed of a different dielectric material than the dielectric backbone grating 206. In an embodiment, the upper dielectric material 230 is composed of a same dielectric material as the lower dielectric material 214. In another embodiment, the upper dielectric material 230 is composed of a different dielectric material than the lower dielectric material 214.

As described in greater detail below, in an embodiment, the resulting structure of Figure 2L enables improved via shorting margins when fabricating later via layers on the structure of Figure 2L. In one embodiment, improved shorting margin is achieved since fabricating a structure with alternating "color" hardmask components reduces the risk of a via shorting to the wrong metal line. In one embodiment, self-alignment is achieved since the alternating color hardmask components are self-aligned to alternating ones of the conductive lines 212. In a particular embodiment, the first hardmask component 222 and second hardmask component 226 are different ones of materials such as, but not limited to, S1O2, Al-doped Si0 ₂ , SiN, SiC, SiCN, SiCON, or metal oxides (such as AlOx, HfOx, ZrOx, TiOx).

Referring to Figure 2M, an inter-layer dielectric (ILD) material layer 234 is formed above the structure of Figure 2L.

Referring to Figure 2N, an opening 238 is formed in the ILD material layer 234 to form a patterned ILD material layer 236. In an embodiment, the opening 238 is formed in a location selected for conductive via fabrication for a next level metallization layer. In contrast to conventional via location selection, the opening 238 can, in one embodiment, have a relatively relaxed width (W) as compared to the width of the corresponding conductive line 212 onto which the conductive via will ultimately be formed. Such an accommodation for a relatively wider via opening 238 can relax constraints on the lithography process used to form the opening 238.

Additionally, tolerance for mis-alignment may be increased as well. Referring again to Figure 2N, a portion of the first hardmask component 222 is removed to expose one of the first of alternating ones of the conductive lines 212, e.g., by a selective wet etch or dry etch process.

Referring to Figure 20, a conductive via 240 is formed aligned with and electrically coupled to the one of the first of alternating ones of the conductive lines 212. In a specific embodiment, a portion of the conductive via 240 is disposed on one or more exposed portions of the second hardmask components 226, as is depicted in Figure 20. In an embodiment, then, an improved shorting margin is realized.

Referring again to Figure 20, in an exemplary illustrative embodiment, an integrated circuit structure includes a plurality of alternating first and second conductive lines 212 along a same direction of a back end of line (BEOL) metallization layer in an inter-layer dielectric (ILD) structure 206/230 above a substrate 202. Each of the plurality of alternating first and second conductive lines 212 is recessed relative to an uppermost surface of the ILD structure 206/230. The ILD structure 206/230 includes a plurality of first 206 and second 230 ILD lines alternating with the alternating first and second conductive lines 212. The first 206 and second 230 ILD lines differ in composition from one another. A first hardmask component 222 is on and aligned with the first conductive lines (first ones of lines 212). A second hardmask component 226 is on an aligned with the second conductive lines (second ones of lines 212). The first 222 and second 226 hardmask components differ in composition from one another. A conductive via 240 is in an opening in the first hardmask component 222 and on one 212' of the first conductive lines 212, as depicted in Figure 20. A portion of the conductive via 240 is on an adjacent one of the first ILD lines 206 and on an adjacent one of the second ILD lines 230, as is also depicted in Figure 20.

Alternatively, although not shown, in another embodiment, a conductive via is in an opening in the second hardmask component 226 and on one of the second conductive lines 212. A portion of the conductive via is on an adjacent one of the first ILD lines 206 and on an adjacent one of the second ILD lines 230.

In an embodiment, the first ILD lines 206 have a bottom below a bottom of the second ILD lines 230, as is depicted in Figure 20. In one such embodiment, the bottom of the second ILD lines 230 is on an ILD material layer 214, with a seam 232 between the bottom of the second ILD lines 230 and the ILD material layer 214, as is depicted in Figure 20. In a specific embodiment, the seam 232 is substantially co-planar with a top surface of the first and second conductive lines 212, as is depicted in Figure 20. In an embodiment, the ILD material layer has a bottom substantially co-planar with the bottom of the first ILD lines 206, as is depicted in Figure 20.

In an embodiment, the ILD material layer 214 and the second ILD lines 230 differ in composition from one another. In one such embodiment, the ILD material layer 214 and the first ILD lines 230 differ in composition from one another. In another embodiment, the ILD material layer 214 and the second ILD lines 230 have a same composition.

In an embodiment, the first 206 and second 230 ILD lines, the first hardmask component

222, and the second hardmask component 226 all have a substantially co-planar upper surface, as is depicted in Figure 20. In an embodiment, the integrated circuit structure further includes a second ILD material layer 236 above the first 206 and second 230 ILD lines, the first hardmask component 222, and the second hardmask component 226, and the conductive via 240 is further in an opening 238 of the second ILD material layer 236, as is depicted in Figure 20.

In an embodiment, the conductive via 240 is further on the second hardmask component 226 of a next adjacent second conductive line 212, as is depicted in Figure 20. Alternatively, as mentioned above, in another embodiment, a conductive via is in an opening in the second hardmask component 226 and on one of the second conductive lines 212. A portion of the conductive via is on an adjacent one of the first ILD lines 206 and on an adjacent one of the second ILD lines 230. In one such alternative embodiment, the conductive via is further on the first hardmask component 222 of a next adjacent second conductive line.

In an embodiment, although not shown, one of the plurality of alternating first and second conductive lines 212 is coupled to an underlying conductive via structure. In one such embodiment, the underlying conductive via structure is connected to an underlying metallization layer of the integrated circuit structure.

A resulting structure such as described in association with Figure 20 may subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure of Figure 20 may represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. Although the above methods (e.g., Figures 2A-20) of fabricating a metallization layer of a BEOL metallization layer have been described in detail with respect to select operations, it is to be appreciated that additional or intermediate operations for fabrication may include standard microelectronic fabrication processes such as lithography, etch, thin films deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, and/or any other associated action with microelectronic component fabrication.

It is to be appreciated that the opening 238 described in association with Figure 2N may have a limited in a dimension going into the page. For example, Figure 3 illustrates a plan view of a portion of an integrated circuit layer representing an operation in a method involving metal spacer and self-aligned conductive via formation for back end of line (BEOL) interconnect fabrication, in accordance with an embodiment of the present disclosure.

Referring to Figure 3, backbone lines 206 and upper dielectric material lines 230 are shown as alternating between alternating first 222 and second 226 hardmask components. An opening in ILD material layer 236 reveals the exposed line 212' . It is to be appreciated that the opening may be representative of opening 238 for a conductive via. Accordingly, in an embodiment, selective removal of a portion of the first hardmask component 222 over a selected line 212' does not reveal the entire underlying line, but rather only a portion of the line where via formation is to occur. It is further to be appreciated that Figure 3 is representative of an embodiment, where the backbone lines 206, the upper dielectric material lines 230, and the alternating first 222 and second 226 hardmask components are formed along a same direction of a back end of line (BEOL) metallization layer.

In another aspect, an angled etch is used for formation of non-via locations above an interconnect. As an example, Figure 4A illustrates a cross-sectional view of a portion of an integrated circuit layer representing an operation in another method involving metal spacer formation for back end of line (BEOL) interconnect fabrication, in accordance with another embodiment of the present disclosure.

Referring to Figure 4 A, a mask 400 is formed over the structure of Figure 2C. Openings 402 are formed in the mask 400. An angled etch process 404 is used to recess select ones of the conductive lines 212 to provide recessed conductive lines 213. The recessed conductive lines 213 are locations where no via connection is made, while the non-recessed lines 212 effectively preserve a via thereon since the lines are not recessed.

The above factors are also relevant for considering placement and scaling of non- conductive spaces or interruptions between metal lines (referred to as "plugs," "dielectric plugs" or "metal line ends" among the metal lines of back end of line (BEOL) metal interconnect structures). Thus, in another aspect, an angled etch is used for formation of a dielectric plug structure.

Figure 4B illustrates a cross-sectional view of a portion of an integrated circuit layer representing an operation in another method involving metal spacer formation for back end of line (BEOL) interconnect fabrication, in accordance with another embodiment of the present disclosure.

Referring to Figure 4B, a mask 450 is formed over the structure of Figure 2C. Openings 452 are formed in the mask 450. An angled etch process 454 is used to completely remove select ones of the conductive lines 212 to provide line end locations 456. The line end locations 456 are locations where no conductive line or via is located, while the non-recessed lines 212 effectively preserve a conductive line or a conductive line and via pairing.

Embodiments described above may be implemented to enable strong self-alignment and mitigation of edge placement issues that otherwise plague conventional patterning.

Embodiments may be implemented to enable robust interconnect reliability and low via/contact resistance.

In an embodiment, as used throughout the present description, an interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (S1O2)), nitrides of silicon (e.g., silicon nitride (S13N4)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In an embodiment, as is also used throughout the present description, metal lines or interconnect line material (and via material) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers, stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form interconnect lines. In an embodiment, the interconnect lines are composed of a barrier layer and a conductive fill material. In one embodiment, the barrier layer is a tantalum or tantalum nitride layer, or a combination thereof. In one embodiment, the conductive fill material is a material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof. The interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, metal lines, or simply interconnect.

In an embodiment, as is also used throughout the present description, hardmask materials

(and in some instances etch stop layers or dielectric plugs or backbone materials) are composed of dielectric materials different from the interlayer dielectric material. In one embodiment, different hardmask materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, a hardmask layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials, such as silicon carbide. Alternatively, other materials known in the art, including materials listed in association with ILD materials, may be used depending upon the particular implementation. Such layers may be formed by CVD, PVD, or by other deposition methods.

It is to be appreciated that the layers and materials described in association with Figures IB, 2A-20, 3, 4A or 4B are typically formed on or above an underlying semiconductor substrate or structure, such as underlying device layer(s) of an integrated circuit. In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the structure depicted in Figures IB, 2A-20, 3, 4A or 4B may be fabricated on underlying lower level interconnect layers.

As described above, patterned features may be patterned in a grating-like pattern with lines, holes or trenches spaced at a constant pitch and having a constant width. The pattern, for example, may be fabricated by a pitch halving or pitch quartering approach. In an example, a blanket film (such as a polycrystalline silicon film) is patterned using lithography and etch processing which may involve, e.g., spacer-based-quadruple-patterning (SBQP) or pitch quartering. It is to be appreciated that a grating pattern of lines can be fabricated by numerous methods, including 193nm immersion lithography (il93), extreme ultra-violet (EUV) and/or electron-beam direct write (EBDW) lithography, directed self-assembly, etc. In other embodiments, the pitch does not need to be constant, nor does the width.

In an embodiment, pitch division techniques are used to increase a line density. In a first example, pitch halving can be implemented to double the line density of a fabricated grating structure. Figure 5 A illustrates a cross-sectional view of a starting structure following deposition, but prior to patterning, of a hardmask material layer formed on an interlayer dielectric (TLD) layer. Figure 5B illustrates a cross-sectional view of the structure of Figure 4 following patterning of the hardmask layer by pitch halving.

Referring to Figure 5A, a starting structure 500 has a hardmask material layer 504 formed on an interlayer dielectric (TLD) layer 502. A patterned mask 506 is disposed above the hardmask material layer 504. The patterned mask 506 has spacers 508 formed along sidewalls of features (lines) thereof, on the hardmask material layer 504.

Referring to Figure 5B, the hardmask material layer 504 is patterned in a pitch halving approach. Specifically, the patterned mask 506 is first removed. The resulting pattern of the spacers 508 has double the density, or half the pitch or the features of the mask 506. The pattern of the spacers 508 is transferred, e.g., by an etch process, to the hardmask material layer 504 to form a patterned hardmask 510, as is depicted in Figure 5B. In one such embodiment, the patterned hardmask 510 is formed with a grating pattern having unidirectional lines. The grating pattern of the patterned hardmask 510 may be a tight pitch grating structure. For example, the tight pitch may not be achievable directly through conventional lithography techniques. Even further, although not shown, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the patterned hardmask 510 of Figure 5B may have hardmask lines spaced at a constant pitch and having a constant width relative to one another. The dimensions achieved may be far smaller than the critical dimension of the lithographic technique employed. Accordingly, a blanket film may be patterned using lithography and etch processing which may involve, e.g., spacer-based-double-patterning (SBDP) or pitch halving, or spacer-based-quadruple-patterning (SBQP) or pitch quartering.

It is to be appreciated that other pitch division approaches may also be implemented. For example, Figure 6 illustrates cross-sectional views in a spacer-based-sextuple-patterning (SBSP) processing scheme which involves pitch division by a factor of six. Referring to Figure 6, at operation (a), a sacrificial pattern X is shown following litho, slim and etch processing. At operation (b), spacers A and B are shown following deposition and etching. At operation (c), the pattern of operation (b) is shown following spacer A removal. At operation (d), the pattern of operation (c) is shown following spacer C deposition. At operation (e), the pattern of operation (d) is shown following spacer C etch. At operation (f), a pitch/6 pattern is achieved following sacrificial pattern X removal and spacer B removal.

In an embodiment, lithographic operations are performed using 193nm immersion litho (il93), EUV and/or EBDW lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti -reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CUM) layer and the anti -reflective coating layer is a silicon ARC layer.

In another aspect, one or more embodiments described herein are directed to fabricating semiconductor devices, such as for PMOS and MOS device fabrication. For example, approaches described herein may be implemented to fabricate a self-aligned gate contact used in a metal oxide semiconductor (MOS) device. As an example of a completed device, Figure 7A illustrates a cross-sectional view of a non-planar semiconductor device having a self-aligned gate contact, in accordance with an embodiment of the present disclosure. Figure 7B illustrates a plan view taken along the a-a' axis of the semiconductor device of Figure 7A, in accordance with an embodiment of the present disclosure.

Referring to Figure 7A, a semiconductor structure or device 700 includes a non-planar active region (e.g., a fin structure including protruding fin portion 704 and sub-fin region 705) formed from substrate 702, and within isolation region 706. A gate line 708 is disposed over the protruding portions 704 of the non-planar active region as well as over a portion of the isolation region 706. In an embodiment, gate line 708 is formed through subtractive patterning as opposed to, e.g., a replacement gate process.

As shown, gate line 708 includes a gate electrode 750 and a gate dielectric layer 752. In one embodiment, gate line 708 may also include a dielectric cap layer 754. A gate contact 714, and overlying gate contact via 716 are also seen from this perspective, along with an overlying metal interconnect 760, all of which are disposed in inter-layer dielectric stacks or layers 770. Also seen from the perspective of Figure 7A, the gate contact 714 is, in one embodiment, disposed over isolation region 706, but not over the non-planar active regions. In accordance with an embodiment of the present disclosure, the dielectric cap layer 754 is a self-aligned or color hardmask layer, as described above.

Referring to Figure 7B, the gate line 708 is shown as disposed over the protruding fin portions 704. Source and drain regions 704A and 704B of the protruding fin portions 704 can be seen from this perspective. In one embodiment, the source and drain regions 704A and 704B are doped portions of original material of the protruding fin portions 704. In another embodiment, the material of the protruding fin portions 704 is removed and replaced with another

semiconductor material, e.g., by epitaxial deposition. In either case, the source and drain regions 704A and 704B may extend below the height of dielectric layer 706, i.e., into the sub-fin region 705.

In an embodiment, the semiconductor structure or device 700 is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines 708 surround at least a top surface and a pair of sidewalls of the three-dimensional body.

Substrate 702 may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, substrate 702 is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof, to form active region 704. In one embodiment, the concentration of silicon atoms in bulk substrate 702 is greater than 97%. In another embodiment, bulk substrate 702 is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. Bulk substrate 702 may alternatively be composed of a group ΙΠ-V material. In an embodiment, bulk substrate 702 is composed of a ΙΠ-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, bulk substrate 702 is composed of a ΙΠ-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

Isolation region 706 may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, the isolation region 706 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

Gate line 708 may be composed of a gate electrode stack which includes a gate dielectric layer 752 and a gate electrode layer 750. In an embodiment, the gate electrode 750 of the gate electrode stack is composed of a metal gate and the gate dielectric layer 752 is composed of a high-K material. For example, in one embodiment, the gate dielectric layer 752 is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of the substrate 702. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 752 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride.

In an embodiment, the gate electrode layer 750 of gate line 708 is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-workfunction-setting fill material formed above or within a metal workfunction-setting layer. The gate electrode layer may consist of a P-type workfunction metal or an N-type workfunction metal, depending on whether the transistor is to be a PMOS or an MOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV. In an embodiment, the dielectric cap layer 754 is composed of a material such as described above in association with hardmask components 222 or 226.

Spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

Gate contact 714 and overlying gate contact via 716 may be composed of a conductive material. In an embodiment, one or more of the contacts or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal -semi conductor alloy (e.g., such as a silicide material). In accordance with another embodiment of the present disclosure, the gate contact 714 is a self- aligned gate contact.

In an embodiment (although not shown), providing structure 700 involves formation of a contact pattern which is essentially perfectly aligned to an existing gate pattern while eliminating the use of a lithographic step with exceedingly tight registration budget. In one such

embodiment, this approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts.

Referring again to Figure 7A, the arrangement of semiconductor structure or device 700 places the gate contact over isolation regions. Such an arrangement may be viewed as inefficient use of layout space. In another embodiment, however, a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region. In general, prior to (e.g., in addition to) forming a gate contact structure (such as a via) over an active portion of a gate and in a same layer as a trench contact via, one or more embodiments of the present disclosure include first using a gate aligned trench contact process. Such a process may be implemented to form trench contact structures for semiconductor structure fabrication, e.g., for integrated circuit fabrication. In an embodiment, a trench contact pattern is formed as aligned to an existing gate pattern. By contrast, conventional approaches typically involve an additional lithography process with tight registration of a lithographic contact pattern to an existing gate pattern in combination with selective contact etches. For example, a conventional process may include patterning of a poly (gate) grid with separate patterning of contact features.

It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such as a trigate device, an independently accessed double gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at a 10 nanometer (10 nm) or smaller technology node.

Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

Figure 8 illustrates a computing device 800 in accordance with one implementation of the disclosure. The computing device 800 houses a board 802. The board 802 may include a number of components, including but not limited to a processor 804 and at least one

communication chip 806. The processor 804 is physically and electrically coupled to the board 802. In some implementations the at least one communication chip 806 is also physically and electrically coupled to the board 802. In further implementations, the communication chip 806 is part of the processor 804.

Depending on its applications, computing device 800 may include other components that may or may not be physically and electrically coupled to the board 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The communication chip 806 enables wireless communications for the transfer of data to and from the computing device 800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 806 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 800 may include a plurality of communication chips 806. For instance, a first communication chip 806 may be dedicated to shorter range wireless

communications such as Wi-Fi and Bluetooth and a second communication chip 806 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more structures, such as metal spacers and corresponding conductive vias, built in accordance with implementations of embodiments of the disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. In accordance with another implementation of the disclosure, the integrated circuit die of the communication chip includes one or more structures, such as metal spacers and corresponding conductive vias, built in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device 800 may contain an integrated circuit die that includes one or more structures, such as metal spacers and corresponding conductive vias, built in accordance with implementations of embodiments of the disclosure.

In various implementations, the computing device 800 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 800 may be any other electronic device that processes data.

Figure 9 illustrates an interposer 900 that includes one or more embodiments of the disclosure. The interposer 900 is an intervening substrate used to bridge a first substrate 902 to a second substrate 904. The first substrate 902 may be, for instance, an integrated circuit die. The second substrate 904 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 900 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 900 may couple an integrated circuit die to a ball grid array (BGA) 906 that can subsequently be coupled to the second substrate 904. In some embodiments, the first and second substrates 902/904 are attached to opposing sides of the interposer 900. In other embodiments, the first and second substrates 902/904 are attached to the same side of the interposer 900. And in further embodiments, three or more substrates are interconnected by way of the interposer 900.

The interposer 900 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group ΙΠ-V and group IV materials.

The interposer may include metal interconnects 908 and vias 910, including but not limited to through-silicon vias (TSVs) 912. The interposer 900 may further include embedded devices 914, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 900. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer 900.

Thus, embodiments of the present disclosure include metal spacer-based approaches for conductive interconnect and via fabrication, and the resulting structures.

Example embodiment 1 : An integrated circuit structure includes a plurality of alternating first and second conductive lines along a same direction of a back end of line (BEOL)

metallization layer in an inter-layer dielectric (ILD) structure above a substrate. Each of the plurality of alternating first and second conductive lines is recessed relative to an uppermost surface of the ILD structure. The ILD structure includes a plurality of first and second ILD lines alternating with the alternating first and second conductive lines. The first and second ILD lines differ in composition from one another. A first hardmask component is on and aligned with the first conductive lines. A second hardmask component is on an aligned with the second conductive lines. The first and second hardmask components differ in composition from one another. A conductive via is in an opening in the first hardmask component and on one of the first conductive lines. A portion of the conductive via is on an adjacent one of the first ILD lines and on an adjacent one of the second ILD lines.

Example embodiment 2: The integrated circuit structure of example embodiment 1, wherein the first ILD lines have a bottom below a bottom of the second ILD lines.

Example embodiment 3 : The integrated circuit structure of example embodiment 2, wherein the bottom of the second ILD lines is on an ILD material layer, with a seam between the bottom of the second ILD lines and the ILD material layer, the ILD material layer having a bottom substantially co-planar with the bottom of the first ILD lines.

Example embodiment 4: The integrated circuit structure of example embodiment 3, wherein the ILD material layer and the second ILD lines differ in composition from one another.

Example embodiment 5: The integrated circuit structure of example embodiment 3 or 4, wherein the ILD material layer and the first ILD lines differ in composition from one another.

Example embodiment 6: The integrated circuit structure of example embodiment 3, wherein the ILD material layer and the second ILD lines have a same composition.

Example embodiment 7: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5 or 6, wherein the first and second ILD lines, the first hardmask component, and the second hardmask component all have a substantially co-planar upper surface.

Example embodiment 8: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6 or 7, further including a second ILD material layer above the first and second ILD lines, the first hardmask component, and the second hardmask component, wherein the conductive via is further in an opening of the second ILD material layer.

Example embodiment 9: The integrated circuit structure of example embodiment 8, wherein the conductive via is further on the second hardmask component of a next adjacent second conductive line.

Example embodiment 10: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7, 8 or 9, wherein one of the plurality of alternating first and second conductive lines is coupled to an underlying conductive via structure, the underlying conductive via structure connected to an underlying metallization layer of the integrated circuit structure.

Example embodiment 11 : A method of fabricating a back end of line (BEOL) metallization layer includes forming a dielectric backbone grating on an etch-stop layer above a substrate. A conformal conductive layer is formed over the dielectric backbone grating. Conductive spacers are formed from the conformal conductive layer, the conductive spacers along sidewalls of the dielectric backbone grating. The conductive spacers are recessed relative to the dielectric backbone grating to form conductive lines along the sidewalls of the dielectric backbone grating. A lower dielectric material is formed on the etch-stop layer between the conductive lines. A first conformal dielectric layer is formed over the dielectric backbone grating, over the conductive lines, and over the lower dielectric material. First dielectric spacers are formed from the first conformal dielectric layer, the first dielectric spacers aligned with the conductive lines. Individual ones of the first dielectric spacers are removed from a second side of the dielectric backbone grating and individual ones of the first dielectric spacers are left on a first side of the dielectric backbone grating opposite the second side to provide a first hardmask component over first of alternating ones of the conductive lines. A second conformal dielectric layer is formed over the dielectric backbone grating, over the first hardmask component, over the conductive lines, and over the lower dielectric material. Second dielectric spacers are formed from the second conformal dielectric layer. Individual ones of the second dielectric spacers are removed from the first side of the dielectric backbone grating and individual ones of the second dielectric spacers are left on the second side of the dielectric backbone grating opposite the first side to provide a second hardmask component over and aligned with second of alternating ones of the conductive lines. An upper dielectric material is formed on the lower dielectric material between the first hardmask component and the second hardmask component. A portion of the first hardmask component is removed to expose one of the first of alternating ones of the conductive lines. A conductive via is formed aligned with and electrically coupled to the one of the first of alternating ones of the conductive lines.

Example embodiment 12: The method of example embodiment 11, wherein removing individual ones of the first dielectric spacers from the second side of the dielectric backbone grating includes using an angled etch process directed at the second side of the dielectric backbone grating.

Example embodiment 13: The method of example embodiment 11 or 12, wherein removing individual ones of the second dielectric spacers from the first side of the dielectric backbone grating includes using an angled etch process directed at the first side of the dielectric backbone grating.

Example embodiment 14: The method of example embodiment 11, 12 or 13, further including, prior to removing the portion of the first hardmask component, forming an inter-layer dielectric (TLD) material layer, and forming an opening in the ILD material layer, wherein the conductive via is further formed in the opening of ILD material layer.

Example embodiment 15: The method of example embodiment 11, 12, 13 or 14, wherein forming the dielectric backbone grating involves using a pitch division patterning process.

Example embodiment 16: A method of fabricating a back end of line (BEOL) metallization layer includes forming a dielectric backbone grating on an etch-stop layer above a substrate. A conformal conductive layer is formed over the dielectric backbone grating.

Conductive spacers are formed from the conformal conductive layer, the conductive spacers along sidewalls of the dielectric backbone grating. The conductive spacers are recessed relative to the dielectric backbone grating to form conductive lines along the sidewalls of the dielectric backbone grating. A lower dielectric material is formed on the etch-stop layer between the conductive lines. A first conformal dielectric layer is formed over the dielectric backbone grating, over the conductive lines, and over the lower dielectric material. First dielectric spacers are formed from the first conformal dielectric layer, the first dielectric spacers aligned with the conductive lines. Individual ones of the first dielectric spacers are removed from a second side of the dielectric backbone grating and individual ones of the first dielectric spacers are left on a first side of the dielectric backbone grating opposite the second side to provide a first hardmask component over first of alternating ones of the conductive lines. A second conformal dielectric layer is formed over the dielectric backbone grating, over the first hardmask component, over the conductive lines, and over the lower dielectric material. Second dielectric spacers are formed from the second conformal dielectric layer. Individual ones of the second dielectric spacers are removed from the first side of the dielectric backbone grating and individual ones of the second dielectric spacers are left on the second side of the dielectric backbone grating opposite the first side to provide a second hardmask component over and aligned with second of alternating ones of the conductive lines. An upper dielectric material is formed on the lower dielectric material between the first hardmask component and the second hardmask component. A portion of the second hardmask component is removed to expose one of the second of alternating ones of the conductive lines. A conductive via is formed aligned with and electrically coupled to the one of the second of alternating ones of the conductive lines.

Example embodiment 17: The method of example embodiment 16, wherein removing individual ones of the first dielectric spacers from the second side of the dielectric backbone grating includes using an angled etch process directed at the second side of the dielectric backbone grating.

Example embodiment 18: The method of example embodiment 16 or 17, wherein removing individual ones of the second dielectric spacers from the first side of the dielectric backbone grating includes using an angled etch process directed at the first side of the dielectric backbone grating.

Example embodiment 19: The method of example embodiment 16, 17 or 18, further including, prior to removing the portion of the second hardmask component, forming an inter- layer dielectric (ILD) material layer, and forming an opening in the ILD material layer, wherein the conductive via is further formed in the opening of ILD material layer.

Example embodiment 20: The method of example embodiment 16, 17, 18 or 19, wherein forming the dielectric backbone grating involves using a pitch division patterning process.