There is a need to be able to capture images at a first sampling rate while providing an accurate representation of the sampled image to output elements at a second sampling rate. In particular, there is a need to reduce the data rate to output elements in order to decrease system power dissipation and data storage requirements in power and storage-sensitive applications, such as preview modes of images in digital cameras.

As the conventional analog signal processing systems are replaced by digital systems, many processes can be compromised to take advantage of inherent benefits of digital processing. For example, it is sometimes necessary to reduce the amount of data captured so that it can be processed efficiently and economically.

Whereas sample rate reduction reduces the amount of data, the widespread use of digital processing in a signal processing system typically requires more power than comparable analog systems. Subsampling the input signal after the analog to digital conversion has the drawback of requiring high power dissipation in upstream analog to digital conversion subsystems that work at a higher clock rate. Subsampling at any stage reduces information content at the expense of signal fidelity, such as increased noise and coarser granularity in processed images.

What is needed is a technique for reducing the data rate in a digital image acquisition system white saving power and without a correspondingly large reduction in signal fidelity.

SUMMARY OF THE INVENTION According to the invention, in a digital image processing device such as a portable digital camera, an analog decimation circuit is provided as a front end for the digital video imaginez circuit so that the data rate is reduced without substantial loss in fidelity so that power dissipation is minimized. In a decimation circuit, the data rate is reduced by reducing only higher frequency spectral components of a captured image without substantial loss in fidelity of the remaining spectral components of the captured image. The required amount of digital data processing is so substantially reduced that

considerable power savings result. A mixture of decimation modes may be effected using the same circuit.

The invention will be better understood by reference to the following detailed description in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of an analog decimation subsystem according to the invention.

Fig. 2 is a circuit diagram of one form of analog decimation subsystem functional in both 1/3 and % 2 decimation modes.

Fig. 3 is a timing diagram of an analog decimation process for 9 input samples in a 1/3 decimation mode.

Fig. 4 is a timing diagram of an analog decimation process for 8 input samples in a 1/2 decimation mode.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS Reference is made to Fig. 1, which shows a block diagram of a decimator 10 according to the invention. A plurality of video input paths Vin (l) through Vin (N) are coupled to a common video signal input Vin (t) and provide signals to N number of sample and hold amplifiers (S/H) 12, all of which are under control of a synchronous clock 14 having a clock rate of fclk. The outputs of the S/H amplifiers 12 are summed at a clocked summing amplifier 16, which itself is under synchronous control of clock 14.

However it is clocked at a rate of fclk/N. The output is a sequentially clocked analog signal Vout suitable for direct conversion to a sequence of digital samples. The output signal at each output clock 1/N is an average over an N sample window.

Referring to Fig. 2, there is shown an example of a programmable analog decimator 100 illustrating the principle of analog decimation and averaging using switched capacitors of value C and 2C. The reasoning behind this evident disparity of values will be apparent hereinafter. A plurality of sampling modules, as represented by sampling module 101, each includes a plurality of switches 102,103,105 and 107 and an analog value storage capacitor 104 of either value C or value 2C.

In this embodiment, ping-pong processing is employed such that two separate output signals are multiplexed in time and share a common output amplifier 160.

While ping-pong processing is not a necessary element of the invention, it provides certain practical advantages. Ping-pong processing, among other advantages, allows extra

settling time for the amplifier 160, reduces power dissipation, and avoids missing input data samples in the hold/amplify mode white the alternate bank is in the sampling mode.

With pins-pont processing, no input samples are missed, and settling time is adequate for a typical operational amplifier at the sampling rates of interest. In proper operation, phases (D5 and (P6 are nonoverlapping and phases 011 and 012 are nonoverlapping and the other phases of each set (respectively 01-04 ; 07-010) must have ended first.

In operation, the ping bank is controlled by switches with phases #1-#6, while the pong bank is controlled by switches with phases d) 7- (P12. A first gating subsystem 1 10 and a second gating subsystem 112 alternately route the feedback signals and ultimately establish the stage gain. Reference is made to the timing diagrams of Fig.

3 and Fig. 4 for a more detailed understanding of operation of the circuit. According to the invention, 1/3 decimation and lX2 decimation can be perfonmed by the same sampling system by proper choice of capacitance values and phasing whereby parallel paths are selectively combined.

Fig. 3 illustrates timing for analog decimation in the 1/3 decimation mode.

The phases of the switches are indicated by the index on the term 0. During a first set of phases, sampling takes place. During a second set of phases, signal averaging and decimation occur.

In the ping or even set of phases, the first analog input sample is stored on capacitor 104 during phase #1. During phase 02 (which is the same as phase #3 in 1/3 decimation mode), the second analog input sample is stored on capacitor 108 (and on capacitor 116 in 1/3 decimation mode). During phase 04, the third analog input sample is stored on capacitor 120. Phase #5 overlaps phases #1,#2,#3 and #4. Phase 05 in used to discharge the feedback capacitor 122 and prepare it for the subsequent averaging phase.

Phase (P6 is used for averaging together the signal samples which were captured during phases (PI, 02, 03 and 04. During phase 06, all of the sampling capacitors 104,108, 116 and 120 are simultaneously switched into the input port of amplifier 160 to produce an output signal at output port 161 which is the sum of the charge on the capacitors 104,108,116 and 120 divided by the capacitance value on first feedback capacitor 122 in first gating subsystem 110, which has been enabled to provide feedback. In this embodiment the values of capacitors 104, and 120 are the same and are

also equal to the sum of the values of capacitors 108 and 116. As a result, in this embodiment, the three input samples have equal weight in the output value. Moreover, the sum of all of the values of the sampling capacitors 104,108,116 and 120 is equal to the value of the feedback capacitor 122, yielding unity gain. In alternative embodiments, the weighting and the gain can be modifie. to tailor the transfer characteristics.

A similar complementary set of phases is employed to process signal samples during the odd or pong phase set.

One-half decimation mode processing operates as follows, as illustrated in Fig. 4.

During a first set of phases, sampling takes place. During a second set of phases, signal averaging and decimation occur.

In the ping or even set of phases, the first analog input sample is stored on capacitor 104 during phase 01 (and on capacitor 108 during phase 02 which is the same as phase #1). During phase 03 (which is the same as phase 04 ion 1/2 decimation mode), the second analog input sample is stored on capacitor 116 (and on capacitor 120 in 1/2 decimation mode). Phase 05 overlaps phases #1, 4) 9, #3 and #4. Phase 05 in Phase 4>5is discharge the feedback capacitor 122 and prepare it for the subsequent averaging phase.

Phase fi6 is used for averaging together the signal samples which were captured during phases 01/02, and 03/04. During phase 06, all of the sampling capacitors 104,108,116 and 120 are simultaneously switched into the input port of amplifier 160 to produce an output signal at output port 161 which is the sum of the charge on the capacitors 104,108,116 and 120 divided by the capacitance value on first feedback capacitor 122 111 first gating subsystem 110, which has been enabled to provide feedback. In this embodiment the values of capacitors 104, and 120 are the same and are also equal to the sum of the values of capacitors 108 and 116. As a result, in this embodiment, the two input samples have equal weight in the output value. Moreover, the sum of all of the values of the sampling capacitors 104,108, 116 and 120 is equal to the value of the feedback capacitor 122, yielding unity gain. In alternative embodiments, the weighting and the gain can be modifie. to tailor the transfer characteristics.

Similarly the capacitors in the pong portion of the circuit are activated in the odd set of phases.

It is noteworthy that the configuration of capacitors having values of 2C, C, C, 2C enables the implementation of both 1/3 decimation and 1/2 decimation modes

with the same hardware. Only the timing of the clock 14 needs to be altered, which can be done as often as every other set of phases.

Selecting different values of capacitance for the sampling modules allows different averaging weights for the output samples, thus changing the transfer characteristics of the filter.

While only a single ended circuit is shown in Fig. 2, it should be understood that the circuit may be fully differential.

The invention has been explained with reference to specific embodiments.

Other embodiments bill be apparent to those of ordinary skill in the art. It is therefore not intended that this invention be limited, except as indicated by the appended claims.