METHOD AND APPARATUS FOR FABRICATING PRINTED CIRCUIT BOARDS The present invention relates generally to methods and apparatus for fabricating a printed circuit board. In one aspect the present invention relates to the fabricating of multi-layer printed circuit boards having at least one via or through-hole. In another aspect, the invention relates to photoprocessing techniques for manufacturing printed circuit board. In yet another aspect, the invention relates to electrodeposition of metal onto printed circuit boards. Considering a first aspect of the present invention, multi-layer printed circuit boards have found increasing use in the manufacture of electronic products. A typical multi-layer circuit board comprises a plurality of individual circuit boards laminated together. Each printed circuit board comprises an electrically non- conductive substrate material having conductive patterns formed on one or both sides thereof. The conductive patterns provide interconnect paths among the active and passive electronic components mounted on the board. In order to afford proper connections, predetermined points on the conductive paths on different individual boards must be interconnected, and these interconnections are typically made by drilling holes through the board at precise locations, followed by plating the through-holes with an electrically conductive material. Since a typical multi-layer board may have a large number of holes, the drilling typically is accomplished using a computer- controlled automatic drilling apparatus. A typical drilling apparatus used for this purpose has multiple drill spindles which are independently activated by the master program in order to reduce the total drilling time required to form the multiple holes on a single multi- layer board. In order to properly position the multi- layer board initially in the drilling apparatus, some

fixed referencing arrangement is usually employed, such as registration holes formed in edge portions of the board which mate with pins carried by the drilling apparatus table. A problem encountered in the multi-layer board fabrication art is that of misregistration among the individual boards comprising the assembly. While the individual board patterns can be formed very precisely using conventional photolithography, exact registration among the multiple patterns on the several boards is impossible to achieve due to distortions introduced during the lamination processing. These distortions typically lead to maximum misregistration at the outer edges of the panels. The principal criterion for a useful board can be simply stated: each hole drilled through the multi-layer board must be surrounded by a conductive material at each layer in order to form a useful hole. Due, however, to the misregistration introduced during the lamination process, this criterion cannot be met by all multi-layer boards. In fact, the rejection rate for multi-layer boards has a present practical range of from 5% to 20%, depending upon the minimum pattern line width, maximum acceptable hole diameter, pattern complexity, and number of layers. In the past, attempts at quality control for multi- layer circuit boards have centered about an inspection process wherein the developing multi-layer board is photographed at preselected stages of the fabrication process using an x-radiation sensitive film and an x- radiation source. After the films are developed, the successive photographs are compared to discern the degree of misregistration or distortion introduced during the intervening steps between the preselected stages. Once final multi-layer assembly is completed, and before the board is subjected to programmed drilling, a final comparison is made and the board is either accepted or

rejected for drilling based upon this final comparison. Although useful, this process is slow and cumbersome and can only effectively be employed to sample representative multi-layer boards with theoretically identical patterns, which are undergoing multi-layer lamination. Since this technique is only amenable to spot sampling in a production environment, many multi-layer boards which should be rejected for misregistration or deformation may be passed on to the automatic drilling station, where they are uselessly drilled and ultimately scrapped. The automated drilling of a board which does not meet the minimum registration requirements is wasteful, since it results in a product which cannot be used. With relatively dense boards, thousands of holes may be drilled, which consumes relatively large periods of the drilling machine time. For example, in an 18 inch X 24 inch multi-layer board, the number of holes typically ranges from 12,000 to 14,000, and the complete drilling of such a board can take as long as 90 minutes. As a result, the x-radiation source/x-radiation sensitive film inspection process has not been found to be a satisfactory solution to the problem of effective quality control for multi-layer boards prior to drilling. In an effort to avoid the disadvantages with the x- radiation source/x-radiation sensitive film inspection process, a system has been developed to permit on-line inspection of multi-layer boards using an x-ray imaging system which examines test holes formed near the corners of the individual board layers and displays the percent of registration among all corresponding holes in a given corner region. While useful, this system is very large and expensive, and merely provides a percent registration figure for each set of test holes on a sequential basis. If a given multi-layer board falls within the permitted percentage of misregistration, it will be passed on for drilling. For those accepted boards which are close to

the maximum permitted misregistration, the accumulation of tolerance errors inherent in the drilling machine can result in a multi-layer board with unacceptable through- holes. The foregoing discussion of the prior art is taken largely from U.S. Patent 4,790,694 to Wilent et al who propose registering a multi-layer printed circuit board prior to drilling by positioning the multi-layer board in an inspection fixture, examining a plurality of target areas located at predetermined locations on the multi- layer board with a radiation source and a detector, comparing the locations of the target areas with predetermined location coordinates, and marking the multi- layer board with reference indicia to provide proper positioning of the multi-layer board during drilling. Preferably, according to Wilent et al, the comparison is performed using predetermined location coordinates obtained by centering a master template having the target areas in the inspection fixture, and storing the location coordinates of the master template target areas. Further preferably, the marking step includes the formation of apertures along one edge portion of the multi-layer board. While Wilent et al is believed to overcome certain of the deficiencies of the prior art as above discussed, Wilent et al employs relatively slow electromechanical servo-motors to move the master template in conjunction with another electromechanical device, the marking mechanism, which slows the process considerably. Moreover, the template itself is subject to warping, misalignment, and design tolerance errors. Finally, marking the multi-layer board with reference indicia in the form of apertures may result in connection lines being inadvertently commoned, shorted, or otherwise compromised. Other problems common to multi-layer drilling systems include drilling inaccuracies due to drill bit wear and chipping, drill bit warping due to bit overheating, drill

smear and machine down-time and rework costs due to drill bit breakage. The present invention in one aspect provides a method for fabricating a through-hole in a multi-layer printed circuit board by separately drilling each layer. Undersized through-holes are formed in predetermined positions in each layer. The separate boards are then stacked and laminated to one another, and the through- holes are then dressed out to finish size. In a preferred embodiment of the invention exact hole positions of developing multi-layer boards are sensed, and adjustments made in imaging subsequent boards. For a further understanding of the nature and advantages of this one aspect of the present invention, reference should be made to the following Detailed Description, taken in conjunction with the accompanying drawings, where like numerals represent like elements, and wherein: Figure 1 depicts a side elevational-exploded view of a multi-layer printed circuit board, and showing its through-hole construction; Figure 2 is a schematic block diagram of a typical prior art method for forming a through-hole in a multi- layer printed circuit board; Figure 3 is a schematic block diagram of a preferred embodiment of the present invention; and Figure 4 is a perspective view of a circuit board layer at an interim stage in the process of the present invention. Figure 1 depicts an exploded view of a multi-layer printed circuit board showing typical through-hole construction. A typical multi-layer printed circuit board, generally referred to as 1, comprises a plurality of separate boards 3a, 3b and 3c each having a variety of conductive patterns or lines 5 disposed upon them, and one or more through-holes 9 comprised of separate holes 7a, 7b

and 7c formed respectively in boards 3a, 3b and 3c. It should be understood at the outset, that although Figure 1 depicts a multi-layer circuit board comprising three separate boards the present invention may be used in fabricating a through-hole in a multi-layer circuit board comprising any number of separate layers. Figure 2 is a schematic block diagram of a typical prior art method of forming a through-hole in a multi- layer board. Such prior art method typically comprises forming the separate board layers in known manner at a lithography station 20, registering the separate boards, and laminating the stacked boards at a laminating station 22, and forming a through-hole through all of the stacked boards at once, e.g. by drilling at a drilling station 24. Drilling typically is then followed by cleaning and desmearing at a cleaning station 26, and the cleaned and desmeared holes are then plated through at a plating station 28. Referring to Figure 3, in accordance with the present invention a first board layer is imaged at an imaging station 30. The imaged board is then processed at a processing station 32 where the conductive patterns are formed, and the processed board is then passed to a drilling station 34 which preferably comprises a multi- spindle drilling automatic drilling machine. Alternatively, drilling station 34 may comprise a punch, a laser drill or other hole-making device. The holes formed at drilling station 34 preferably are undersized by design, i.e. typically 50 to 75% of the desired finish hole size. Making the holes initially smaller than the desired finish hole size has the advantage of reducing wear on the larger drill bits, and coupled with a finish drilling step may produce a neater/cleaning final hole. However, it is not necessary to make the holes initially smaller than the desired finish hole size. The board, following drilling, is then passed to a

stacking and laminating station 42 where a plurality of boards are laminaterd together to produce a developing multi-layer board. The developing board is then passed to a measuring station 36 wherein one or more of preselected hole positions are sensed, for example, using a light or x-ray or other source 38 and receptors 40 (Fig. 4) which determine the actual position(s) of the selected holes. Measurements of hole positions taken at measuring station 36 are then fed to a computer driven imager at imaging station 30 which "distorts" or adjusts the computer generated image to accommodate for variations of through-hole positions based on the actual observed position of the holes using digital imaging or conformal mapping techniques to image the next board or series of board layers, e.g., in accordance with the teachings of U.S. Patent Nos. 4,639,868, 4,815,000 and 5,005,135, the teachings of which patents are incorporated herein by reference. The next imaged board layer or layers is/are then passed to processing station 32 where the circuits, etc. are formed as before, and the next processed board layers is/are then passed to drilling station 34, where the individual board layers are drilled as before. The resulting drilled boards are then passed to stacking and lamination station 42, wherein the board layers are stacked and laminated in alignment on the developing board. Hole position measurements are taken as before, and the new hole position measurements are fed to the computer driven imager at imaging station 30 where new adjustments are made in the artwork to accommodate variations in the hole positions. The process is repeated until the desired number of layers is achieved. Finally, the through-holes are dressed out at a drilling station 44 to conform substantially to the through-holes predetermined design position and size. Inasmuch as only a small amount of material needs to be

removed in dressing out the through-holes at drilling station 44, the problems of drill bit overheating, excessive wear and breakage, and drill smear, present in conventional multi-layer drilling operations are avoided. Also, since hole misregistration is essentially eliminated, board loss due to drilling error also essentially is eliminated. Separately drilling the individual board layers in accordance with the present invention also permits drilling within the aspect ratio of the drill bits, thus substantially reducing drilling problems of drill bit overheating, drill bit excessive wear and breakage, machine down-time and drill bit costs of conventional multi-layer drilling systems, as well as board loss or rework costs resulting from worn or broken drill bits and drill smear. Thus, even though more individual drilling operations and board handling may be required, the overall cost of separately drilling each board is less than drilling a stack of boards when down-time and board loss is figured in. While the above description provides a full and complete disclosure of the preferred embodiment of the invention, various modifications may be made. For example, while it is preferred to separately drill the individual board layers, two or three board layers may be clamped together and drilled simultaneously in accordance with the teachings of the present invention. Also, the invention also may advantageously be employed to produce buried vias in a multi-layer board. Still other modifications will be apparent to one skilled in the art. For example, the process of the present invention also advantageously may be used to correct artwork to compensate for lamination distortion based on examination, for example, of alignment marks using lights or x-rays. Similarly, the process of the present invention may be used to measure the effects of

lamination distortion in advance using test artwork such as patterns of fiducial marks (rather than the actual board artwork). Thus, by deriving a model for the lamination error introduced into, for example, a 6x12 board of a particular thickness and material, it should not be necessary (other than for spot quality control checks) to measure the lamination effects in a specific 6x12 board of similar thickness and material, even if the artwork is different. In other words, using the process of the present invention, it is possible to use the measurements from one "master" 6x12 board to alter the artwork of all subsequent 6x12 boards, even if the subsequent boards have different artwork. Another possible test pattern would be to fabricate a through-hole that only connects to one layer of the board. In other words, only one layer has the "hole surround" copper area. This would make it possible to distinguish the offset of one particular layer from the offset of the other layers allowing for correction of lamination distortion that varies in severity by board layer. Turning now to another aspect of the present invention, the ongoing integration and miniaturization of components for electronic circuitry has become a growing challenge to the limits of printed wiring board technology over the last twenty years. Printed circuit boards or printed wiring boards (PWB) as they are more commonly termed, play several key roles. First, the electrical components, such as specially packaged integrated circuits, resistors, etc., are mounted or carried on the surface of the flat usually sturdy card-like board. Thus, the PWB serves as a support for the components. Secondly, using chemically etched or plated conductor patterns on the surface of the board, the PWB forms the desired electrical interconnections between the components. In addition, the PWB can include a metal area serving as a heat sink.

Conductor patterns typically are formed by photoetching a copper foil clad epoxy fiberglass substrate. A photoresist layer is applied to the copper foil and patterned by exposure to ultraviolet (UV) light projected through a mask, often referred to as "artwork", e.g., to a positive art work image of the circuit pathways and contacts. Those areas exposed to the light are altered and are removed by treatment with a solvent for the resist, leaving areas of copper, e.g., in the desired conductor pattern, underneath the protective barrier of the remaining photoresist. The exposed copper is etched away and the remaining photoresist is then chemically removed to expose the resulting conductor pattern. Alternatively, the photoresist can be patterned to form channels for electroless plating of conductor patterns. There are, of course, many variations on this procedure, but all of them require photo-patterning of the resist layer. Increased use of integrated circuits, and surface mount technology (SMT) has accelerated the densification of electronic circuitry. Surface mount devices (SMD) are applied directly to the surface of the PWB and soldered using vapor phase, infra-red (IR) or other mass soldering techniques. SMT is revolutionizing the electronic manufacturing industry by reducing assembly cost by about 50%, increasing component density by over 40% and enhancing reliability. The array of terminals on SMD' s has a higher density or finer pitch then those on conventional components. As each terminal still has to be properly electrically connected to the respective conductor on the board, registration of SMD' s requires high resolution for the PWB conductor lines. Indeed, SMD circuitry has become so dense that double-sided boards cannot accommodate all of the needed electrical connections. Thus, multilayer PWB's have become the focus of attention and several competing technologies are

evolving. Those techniques which rely on stacks or layers of conductor patterns have interlayer registration requirements in additional to the exacting line width and spacing of a conductor pattern in a given layer. Manufacturing very fine lines on the order of 3 to 5 mils in registration over four or more layers deep is very difficult. To take fullest possible advantage of the benefits offered by the emerging SMT, new fabrication processes must be developed in the manufacture of substrates and boards. In the past, one of the problem areas in fabrication of PWB's has been the generation and use of artwork masters for patterning the photoresist layers. Using photographic film or glass plates poses inherent difficulties in stability, registration, transport and storage. In order to eliminate artwork masters the industry has fostered the development of UV laser plotters. These machines pattern the UV sensitive resist directly without artwork. Conductor patterns are designed using computer- assisted design (CAD) which digitizes the coordinates and dimensions of all of the paths and converts them to control signals for a UV laser x-y plotter. However UV laser plotters have a number of limitations, particularly when used for fine line, high density work. Principal among these is the fact that UV sensitive resists are relatively insensitive materials, requiring high levels of exposure energy. As a result, line edge resolution is limited. In order to achieve high plot speeds, these systems operate in a raster scan mode. Raster scanning produces considerable edge irregularities which are particularly apparent in plotting angled lines. Limitations in accuracy and minimum line width are characteristic of existing raster plotting systems. Another problem of current raster plotting systems is the short life expectancy of the laser source. A further

problem with direct-from-CAD UV plotting of the photoprocessible layer is that such systems do not permit inspection before polymerization. If an error is made in the plot, the mistake is indelibly embedded in the UV sensitive layer. In the case of a resist, the board may be salvaged only by removing the entire resist layer and starting over after cleaning and baking the board free of moisture a second time. In the case of a UV plotted solder mask, a glitch in the pattern may result in the entire panel being discarded. Also, UV laser plotters are very expensive, and are relatively slow. The foregoing discussion of the prior art is taken largely from Lake et al, U.S. Patent No. 4,666,818 who propose a method for fabricating a printed circuit board utilizing two photo-reactive coatings. According to Lake et al a photo-processable ultraviolet sensitive layer is overlayed with a thin, unexposed, and undeveloped (silver halide) photographic film. A CAD system, containing within it the desired pattern layout for the interconnection lines, drives a white light X-Y plotter to expose the silver halide film on the board in the desired pattern, without effecting the underlying ultraviolet sensitive layer. The film is then developed and used as an in-situ mask for patterning the ultraviolet layer during an exposure of the board to ultraviolet light. The silver halide photographic film is not further affected by the exposure of the board to ultraviolet light. After the ultraviolet exposure, the silver halide photographic film is peeled off, to expose the resist, and the resist-coated board is processed further according to conventional methods. Although capable of producing somewhat respectable interconnection line resolution and definition, the teachings of this patent result in serious drawbacks. First, even though Lake et al. teaches use of a white light x-y plotter and not a UV laser, all of the drawbacks associated with the use of a UV laser, e.g. speed, cost, etc., are presented by Lake et al. Moreover, the presence

of the photographic film substrate introduces optical problems which results in reduced interconnection line definition and resolution due to white light diffusion through the film. The present invention in another aspect provides a system which overcomes the aforesaid and other disadvantages of the prior art by coating a circuit board substrate with a conventional photoresist layer, and directly covering the photoresist layer with a formed iτι situ light sensitive silver halide emulsion layer. The silver halide emulsion layer is then exposed through a mask to a predetermined patterned image by a conventional exposure lamp such as a white light flash tube or the like. Alternatively, the silver halide emulsion may be exposed by a computer driven array scanner, a raster, or the like. The exposed emulsion layer is then developed, whereby to form a patterned image overlaying the photoresist layer. Due to the high definition characteristics of the halide emulsion layer the resulting patterned image forms a high definition mask in direct contact with the resist. The resulting patterned image coated board is then exposed to ultraviolet light. The halide emulsion layer is then stripped, leaving the patterned exposed photoresist layer coated board ready for further processing in accordance with conventional additive processes or in the case of a metallized or foil clad circuit board substrate subtractive processes. For a fuller understanding of the nature and advantages of this other aspect of the present invention reference is made to the enclosed drawings, wherein like numbers depict like parts, and wherein: Figure 5 is a block flow diagram illustrating one process for producing a printed circuit board in accordance with the present invention; and Figures 6 to 14 are diagramatic cross-sectional views of a printed circuit board at various stages of formation

in accordance with the process of the present invention. Referring now to Figs. 5 and 6 of the drawings, conductive layer 103 such as a copper foil cladding or vapor deposited metal layer is disposed at metallizing station 130 on one surface of conventional circuit board substrate base 105, e.g., formed of an electrically insulating material such as glass filled epoxy. Referring also to Figure 7, the metallized surface is then coated at a resist coating station 32 with a conventional photoresist layer 107. Both the material composition and manner of deposition of the photoresist layer should not be viewed restrictively. Rather, it is to be understood that all prior art methods of deposition and all prior art material compositions may be used without departing from the teachings of the present invention. Referring also to Figure 8, after depositing the photoresist layer 107 upon the conductive layer 103 of the circuit board substrate 105, a halide emulsion layer 109 is directly deposited thereon at an emulsion coating station 134. Preferably, the halide emulsion layer comprises photographic grade silver bromide; although other light sensitive silver halides may be used in the instant invention. Also, if desired, one or more light sensitizing agents may be included in the silver halide emulsion in known manner. The metal halide layer may be cast, but preferably is spin coated in order to achieve a thin, uniform coating. The metal halide emulsion layer should be made as thin as possible in order to enhance definition, since resolution and definition of the photoresist layer is essentially a function of the photo- diffusion and distortion characteristics of the halide layer. Preferably, the thickness of the halide layer is 0.1 to 1.0 mil. Referring also to Figure 9, the emulsion-coated board is then passed to a first imaging station 136 where the

coated board is then exposed through a mask 111 having a pattern image that corresponds negatively to the desired pattern of interconnection lines to be embodied. The mask may comprise a photographic plate or other such masking device comprising both opaque regions 115 and transparent regions 113. Advantageously, a single pattern image mask may be reused to produce any number of printed circuit boards. The coated board is exposed to light of a predetermined wavelength to which the silver halide layer is sensitive, e.g. white light, but which light has little or no effect on the underlying photopolymer layer. The light is passed through transparent regions and is prevented from passing through opaque regions of the pattern image mask. Thus, only light striking transparent regions passes through the transparent regions of the pattern image to reach the surface of the halide layer 109. The distance between the pattern image and the surface of the halide layer 109 should be predetermined so as to eliminate optical dispersion and aperturic distortion that may result from placing the pattern mask at a distance that is either too close or too far away from the surface of the halide layer 109. Light that is transmitted through the pattern image strikes and activates only selected areas of halide layer 109. Alternatively, the exposure may be effected by a computer driven array scanner, or raster or the like, which selectively directs light in a predetermined pattern onto the halide layer. The exposed plate is then developed at development station 138 employing conventional silver halide photography development techniques which reduces the activated halide particles to black metallic silver. Halide particles which have not been activated by exposure to light can then be dissolved out of the emulsion in a conventional fixing bath, resulting in an emulsion layer having opaque 117 and transparent regions 119 portions

(Fig. 10). The opaque regions 117 and transparent regions 119 of the emulsion layer 109, in turn function as a mask for the subsequent exposure of the photoresist. Referring also to Figure 11, following development of the halide emulsion layer 109, a conventional UV light is shone onto the surface of the developed halide emulsion layer at a second exposure station 140. Those portions of the photoresist layer 107 that are not covered by opaque regions 117 of the emulsion layer 109 are activated by the light passing through transparent regions 119. The reaction resulting therefrom may be of a polymerization- type or other such photosensitive reaction, depending upon the type of photoresist used. The photosensitive reaction described above thus produces reacted regions 121A, 121B, 121C, and 121D as depicted in Figure 11. Thereafter, the emulsion layer 109 and the unreacted portions of the photoresist layer 107 are removed, e.g. by peeling or stripping the emulsion layer, in a stripping station 42, and then dissolving the unreacted portions of the photoresist in a known manner, in a differential solvent for the resist in a solvent station 144 leaving a structure in which selected areas of the conductive layer 103 are exposed, e.g. as shown in Figure 12. The resulting structure may then be passed to an etching station 46 wherein exposed areas of the conductive layer 103 are removed, while areas (12IE, 12IF, 121G, 121H - Fig. 14) protected by the photoresist remain intact. Finally, the remaining portions of photoresist 121 are removed, in known manner at a resist removal station 148, yielding a substrate having formed therein a predetermined fine line conductive pattern. A feature and advantage of this aspect of the present invention is the ability to achieve extremely fine line definition and high resolution using conventional mass exposure techniques. This feature and advantage follows from the provision of a halide emulsion, directly on the

photoresist. The halide emulsion, after exposure and development, acts as a high definition mask in direct contact with the photoresist. Thus, light scattering, etc. problems of using a conventional separate mask are eliminated. Also, due to the extreme fast exposure time, high definition and resolution achievable using silver halide emulsion, fine line definition may be achieved from a single fixed position light source. Thus, using the instant invention, it is possible to rapidly and inexpensively mass produce printed circuit boards having extremely fine line definition and high resolution, using relatively low cost conventional exposure apparatus. Moreover, exposing the silver halide layer by means of a scanning exposure system or the like facilitates accomodating for pattern errors. The present invention also may be used to produce multi-layer circuit boards. Also, the present invention also may be advantageously used to produce circuit boards employing additive techniques. The invention is subject to modification. For example, although only use of white and UV light are presented above, other wavelengths of light may be used in the process of the present invention without departing therefrom. Thus, the process of the present invention should be viewed broadly, as encompassing use of two (first and second) wavelengths of light for exposing the emulsion layer and masked board, respectively, and not simply white and UV light. Turning now to a third aspect of the invention, electroplating is an established process of producing a metallic coating on a surface. Such coatings may perform a protective function to prevent corrosion of the metal on which they are deposited, e.g., plating with zinc or tin (electro-galvanizing); or a decorative function, e.g., gold or silver plating; or both functions, e.g., chromium plating. The principal of electroplating is that the coating

metal is deposited from an electrolyte, typically an aqueous acid or alkaline solution, onto a target substrate or panel. The latter forms the cathode (negative electrode) while a plate of the metal to be deposited serves as the anode (positive electrode). During a standard electroplating process, the periphery of the printed circuit board, i.e., the portions of the printed circuit board adjacent its outer edges, tends to be at a higher current density than the center of the printed circuit board. Hence, metal deposits more rapidly adjacent the periphery of the printed circuit board than at the center. The result of this is that by the time the metal has deposited at the center of the circuit board to form a desired thickness, the metal deposited adjacent the periphery is at a thickness much greater than the thickness at the center. As a result, the width of depositing metal lines may grow laterally, and the resulting plated lines near the periphery may develop a cross sectional configuration resembling a mushroom. In U.S. Patent No. 4,828,654, it is reported that by spacing the cathode a relatively large distance from the anode, and by making the effective size of the panel to be plated, i.e. the cathode, larger in size than the anode, there is more uniform distribution of the electroplating field. The more uniformly distributed field causes the metallic ions to be electrolytically deposited at a more uniform rate over the articles in the panel. This prior art arrangement reportedly avoids undesirable uneven plating build-up on the articles at those areas where there is a concentration of the electroplating field. It is also reported that field concentrations occur when the size of the article is smaller than the size of the anode, and results in the edges of the article experiencing a substantial greater build up of metallic ions than the center area of the article. Making the effective size of

the cathode (the article to be plated) greater than the size of the anode and spacing the anode a relatively large distance from the cathode, operates to discourage the formation of areas of concentration in the electroplating field and encourages the ion transfer to become more uniform over the entire area of the cathode. U.S. Patent No. 4,828,654 teaches an anode used in electroplating formed by a plurality of individual anode segments which can be selectively energized to establish an effective anode size that relates to the size of the article to be electroplated, thereby establishing an electrical field of more uniform characteristics to transfer ions from the anode to the articles at a more uniform deposition rate over the whole surface of the article. By adjusting the effective size of the anode to correspond and relate to the size of the article, the non- uniform deposition rates associated with concentrated localized field reportedly are avoided, and the physical size of the electroplating apparatus can be reduced. U.S. Patent No. 4,933,061 teaches an electroplating apparatus for electroplating a plurality of items. The patented apparatus includes a tank having a bottom wall and side walls, adapted to hold a predetermined quantity of electrolytic plating solution. A sparger system at the bottom of the tank directs the electrolytic plating solution in an upward direction. A cathode rack supports the items to be electroplated and extends intermediate to the anode plates and upwardly from the sparger system. Strategically placed openings in the anodes and an anode screen in conjunction with the sparger system reportedly act to reduce the plating thickness variance over the rack. In U.S. Patent No. 5,017,275, there is disclosed an anode structure comprising a resilient anode sheet having an active anode surface, and a support sub-structure for the anode sheet. The anode sub-structure has a pre-

determined configuration. By flexing the anode sheet onto the anode sub-structure, so that the anode sheet conforms to the configuration of the anode sub-structure, there reportedly is provided an adequate electrical junction for substantially uniform current distribution. A collection of the known variables which affect the electroplating process have been set out in detail in the HANDBOOK OF PRINTED CIRCUIT MANUFACTURING by Raymond H. Clark (1985). Therein it is reported that the factors which effect the electroplating process include: 1. plating pattern geography; 2. panel thickness and size of plated through holes; 3. panel boarders; 4. plating rack; 5. bath chemistry, e.g., concentration of metals and acids, concentration of organic leveling and brightening agents, concentration of contaminants; 6. bath temperature; 7. anode-cathode spacing; 8. anode current density; 9. anode depletion; 10. plating bath agitation; 11. cathode agitation; 12. rectifier consideration; and 13. the skill and experience of the plater. In accordance with the third aspect of the present invention, a system for electroplating comprises a receptacle for holding a bath of electroplating solution. An electrically conducting anode electrode is positioned within the receptacle in contact with the bath. The anode is covered at least in part with one or more electrically non-conductive masks which operate to direct the electric current as it travels through the electroplating solution to distribute over the cross-sectional surface area of a conductive substrate immersed in the electroplating receptacle at a location spaced apart from the anode to

establish substantially uniform electroplating ion transfer over the surface of the substrate. The mask or masks may be in direct contact with the anode, or in close proximity thereto. Completing the system are means for electrically energizing the anode and completing the circuit to the target/cathode. The overall size of the anode, and the size and shape of the mask or masks, mask openings, number of openings, and location of openings in the non-conductive mask are all selected with reference to the size, target configuration and aspect ratio (anode-to-target) of the article to be electroplated. The distance separating the masked anode from the target panel substrate also is adjusted to promote uniform targeting of the electroplating current. The present invention also provides a method of electroplating an article with a generally uniform thickness coating by covering the anode electrode at least in part with one or more electrically non-conductive masks having a pattern of openings of predetermined configuration relative to the target cathode whereby to result in substantially uniform deposition over the target during electroplating. For a fuller understanding of the nature and aspect of this third aspect of the present invention, reference is made to the enclosed drawings, wherein like numerals depict like parts, and wherein: Figure 15 is a perspective view of an electroplating apparatus embodying the present invention; Figure 16 is a side view of portions of the electroplating system of Figure 15; and Figure 17 is a view similar to Figure 16, and illustrating an alternative form of electroplating system made in accordance with the subject invention. Referring to Figures 15 and 16, the electroplating system 210 includes an outer housing 212 which is

preferably formed of an electrically insulating and corrosion-resistant material such as plastic. The housing 212 includes means in the form of a downward extending receptacle 214 for holding a bath of an electroplating solution 216. By way of example, for electroplating copper, bath 216 may comprise a copper sulfate solution commonly referred to as "acid copper". The plastic material of the housing 212 and receptacle 214 resists the toxic and corrosive effects of the bath 216. The electroplating system 210 includes an anode electrode 215 which is covered at least in part with a non-conductive mask 218 (Figure 16), which will be described in detail below. Mask 218 may be coated directly on the electro-active surface of anode electrode 215 or may comprise a separate element which may be fixed to or suspended in close proximity to the electro-active surface of electrode 215. The anode electrode 215 and mask 218 are suspended from an upper support member 220 which is preferably formed of plastic to resist the corrosive effects of the bath 216 and to provide electrical insulation. The anode electrode 215 and mask 218 are held suspended from the support member 220 by fasteners such as non-corrosive titanium machine screw 222. The article to be plated typically comprises a printed circuit board 226 which becomes the electrical cathode of the electroplating system during electroplating. The printed circuit board 226 is suspended in the bath by a clamp 228 which includes a thumbscrew 230 or other similar fastening device for attaching and suspending or supporting the article to be electroplated in the bath. Clamp 228 in turn is mechanically connected to an electrically insulating support member 234. A handle 236 extends above the support member to allow the printed circuit board to be inserted into and removed from the bath 216 at the start and end of the electroplating

process. Completing the system are electrical conductors 224 and 232 for electrically connecting the anode electrode 225 and cathode target 226 to a direct current or quasi direct current electrical energy source 238. A feature and advantage of the present invention is the ability to substantially and uniformly electroplate the conductor paths, lands and holes of a target printed circuit board. This is accomplished by covering selected areas of the electro-active surface of the anode 215 with a non-conductive mask 218 which directs the electric current through the electroplating solution so that the metal will be deposited onto the target cathode in a controlled manner. The overall size of the anode, and the size and shape of the openings, number of openings, and location of the openings in the non-conductive mask are selected with reference to the size and geometry of the target article to be electroplated, with the result that field concentrations at any location on the target article are avoided, thereby achieving a relatively uniform layer of electroplated material. Typically, the anode mask will have openings which are substantially the negative of the target article; however, in order to compensate for uneven plating buildup on the target panel periphery, the mask openings corresponding to peripheral areas of the target board preferably should be made relatively smaller than corresponding deposition areas on edges of the target board, while the mask openings corresponding to center areas of the target board preferably should be made relatively larger than the corresponding deposition areas on center areas of the target board. Mask size and shape also may be empirically determined using the above criteria. The mask may be applied directly to the anode electro-active surface, for example, by coating, or the mask may comprise a separate element which may be fixed directly to or held in close

proximity to the anode electro-active surface, thereby allowing various selected exposed portions of the anode to serve as a source of field concentration for the electroplating process. The distance between the masked anode and the target printed circuit board should be limited to a relatively short distance, typically 5.08 to 8.89 cm. at normal plating potentials, so that bulk transfer through the electroplating bath does not defeat the masking effect. Certain changes may be made in the above constructions. For example, as shown in Figure 17, it also is possible to achieve uniform deposition by covering the cathode with one or more non-conductive apertured masks. In such case, the mask or masks should be spaced a short distance, e.g. 4.45 to 7.62 cm. from the cathode. Locating the mask less than 4.45 cm. or more than 7.62 cm. from the cathode is not advised and does not achieve uniform deposition.