Title:
METHOD FOR DEFECT INSPECTION AND APPARATUS FOR DEFECT INSPECTION
Document Type and Number:
WIPO Patent Application WO/2011/068056
Kind Code:
A1
Abstract:
Provided is a technique for a wafer inspection conducted by simple operation, which is useful even when the inspection covers a variety of items and the inspection items are changed frequently with time like in a start-up period of a semi-conductor process. According to the technique, inspection images are collected, and then a template is prepared from the inspection images. A plurality of regions are defined on the template, and inspection methods and output indexes are registered in correspondence with the respective regions. In the inspection, by reference to the template images corresponding to the derived inspection images, the inspection is conducted based on the inspection information registered therein and the quantitative output levels are calculated.
Inventors:
NAKAGAKI RYO (JP)
HARADA MINORU (JP)
HIRAI TAKEHIRO (JP)
TAKAGI YUJI (JP)
HARADA MINORU (JP)
HIRAI TAKEHIRO (JP)
TAKAGI YUJI (JP)
Application Number:
PCT/JP2010/070819
Publication Date:
June 09, 2011
Filing Date:
November 22, 2010
Export Citation:
Assignee:
HITACHI HIGH TECH CORP (JP)
NAKAGAKI RYO (JP)
HARADA MINORU (JP)
HIRAI TAKEHIRO (JP)
TAKAGI YUJI (JP)
NAKAGAKI RYO (JP)
HARADA MINORU (JP)
HIRAI TAKEHIRO (JP)
TAKAGI YUJI (JP)
International Classes:
H01L21/66; G01B15/08; G01N23/225; H01J37/22
Foreign References:
| JP2009122046A | 2009-06-04 | |||
| JP2003083908A | 2003-03-19 |
Attorney, Agent or Firm:
POLAIRE I. P. C. (JP)
Polaire Intellectual Property Corporation (JP)
Polaire Intellectual Property Corporation (JP)
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