MISMATCH USING ITERATIVE LOOPS

The present invention generally relates to a method and a device for correcting and/or estimating the mismatch between both in-phase (I) and quadrature-phase (Q) baseband signal components of a received radio-frequency (RF) signal in a radio receiving device. The mismatch between both in-phase and quadrature-phase baseband signal components is usually referred to as in-phase/quadrature-phase mismatch, or shortly as IQ mismatch (IQM) or also IQ imbalance.

A radio receiver uses two distinct orthogonal channels to form the in-phase (I) and the quadrature-phase (Q) components of the received signal. Each channel is composed of at least a mixer, at least one programmable gain amplifier and at least one filter. The mismatch or imbalance between in-phase and quadrature-phase channels regarding the filters, the at least one programmable gain amplifiers and the local oscillators can lead to imperfect phase quadrature, known as IQM phase error, and imperfect gain balancing, known as IQM gain error, between those two channels that may severely limit the performance of the receiver. The present invention aims at providing a method and a device for correcting and/or estimating the mismatch between in-phase and quadrature-phase signal components on a received signal in a radio receiving device in order to improve the performance of the receiver.

To that end, the present invention concerns a method for correcting and/or estimating an in-phase/quadrature-phase mismatch on a random received signal in a radio receiving device, said method causing the device to perform:

- processing the random received signal in order to obtain an in-phase component and a quadrature-phase component,

- amplifying by at least a first programmable gain amplifier and digitally converting by a first analogue to digital converter the in-phase component in order to obtain in-phase samples,

- amplifying by at least a second programmable gain amplifier and digitally converting by a second analogue to digital converter the quadrature-phase component in order to obtain quadrature-phase samples,

- correcting and/or estimating in-phase/quadrature-phase mismatch based on in- phase samples and quadrature-phase samples, the estimating of the in- phase/quadrature-phase mismatch being performed using two estimation loops, each loop generating a coefficient, a gain loop comprising a first weighting module which weights the difference of in-phase samples and of quadrature-phase samples and a phase loop comprising a second weighting module which weights the result of a multiplication of in-phase samples and of quadrature-phase samples, the correcting being performed on in-phase samples and/or quadrature-phase samples using coefficients provided by the loops.

The present invention concerns also an apparatus for correcting and/or estimating an in-phase/quadrature-phase mismatch on a random received signal, comprising:

- means for processing the random received signal in order to obtain an in-phase component and a quadrature-phase component,

- means for amplifying by at least a first programmable gain amplifier and digitally converting by a first analogue to digital converter the in-phase component in order to obtain in-phase samples, - means for amplifying by at least a second programmable gain amplifier and digitally converting by a second analogue to digital converter the quadrature-phase component in order to obtain quadrature-phase samples,

- means for correcting and/or estimating in-phase/quadrature-phase mismatch based on in-phase samples and quadrature-phase samples, the means for estimating the in-phase/quadrature-phase mismatch comprising two estimation loops, each loop providing a coefficient, a gain loop comprising a first weighting module which weights the difference of in-phase samples and of quadrature-phase samples and a phase loop comprising a second weighting module which weights the result of a multiplication of in-phase samples and of quadrature-phase samples, the means for correcting in-phase samples and/or quadrature-phase samples using the coefficients.

The present invention concerns also an apparatus for correcting and/or estimating an in-phase/quadrature-phase mismatch on a random received signal, the apparatus comprising circuitry causing the apparatus to perform:

- processing the random received signal in order to obtain an in-phase component and a quadrature-phase component,

- amplifying by at least a first programmable gain amplifier and digitally converting by a first analogue to digital converter the in-phase component in order to obtain in-phase samples,

- amplifying by at least a second programmable gain amplifier and digitally converting by a second analogue to digital converter the quadrature-phase component in order to obtain quadrature-phase samples,

- correcting and/or estimating in-phase/quadrature-phase mismatch based on in- phase samples and quadrature-phase samples, the estimating of the in- phase/quadrature-phase mismatch being performed using two estimation loops, each loop generating a coefficient, a gain loop comprising a first weighting module which weights the difference of in-phase samples and of quadrature-phase samples and a phase loop comprising a second weighting module which weights the result of a multiplication of in-phase samples and of quadrature-phase samples, the correcting being performed on in-phase samples and/or quadrature-phase samples using coefficients provided by the loops.

Thus, the performance of the receiver is improved. By performing the correction and/or the estimation of the in-phase/quadrature- phase mismatch on in-phase and quadrature-phase samples after all the amplifications, the IQ mismatch gain and phase impairments can be corrected efficiently.

Furthermore, by using two loops for the estimating, the present invention enables a quick and reliable estimation.

By using two coefficients for the correction, the correction is reliable and does not need complex hardware or software implementation.

The present invention also concerns, in at least one embodiment, a radio access network system comprising an apparatus for correcting and/or estimating an in- phase/quadrature-phase mismatch according to the present invention.

The present invention also concerns, in at least one embodiment, a computer program that can be downloaded from a communication network and/or stored on a medium that can be read by a computer or processing device. This computer program comprises instructions for causing implementation of the aforementioned method, or any of its embodiments, when said program is run by a processor.

The present invention also concerns an information storage means, storing a computer program comprising a set of instructions causing implementation of the aforementioned method, or any of its embodiments, when the stored information is read from said information storage means and run by a processor.

The characteristics of the invention will emerge more clearly from a reading of the following description of an example embodiment, the said description being produced with reference to the accompanying drawings, among which:

Fig. 1 schematically represents an example architecture of a receiver device in which some embodiments of the present invention can be implemented;

Fig. 2 illustrates an example of the receiving part of the wireless interface of the receiver according to some embodiments of the present invention;

Fig. 3 schematically represents an example of architecture of an in- phase/quadrature-phase mismatch correction and/or estimation module according to some embodiments of the present invention;

Fig. 4 schematically represents an example of architecture of an in- phase/quadrature-phase mismatch correction module according to some embodiments of the invention; Fig. 5 schematically represents an example of architecture of an in- phase/quadrature-phase mismatch estimation module according to some embodiments of the invention;

Fig. 6 schematically represents an architecture of a sample level detection module according to some embodiments of the invention;

Figs. 7a and 7b schematically represent some examples of loops weight values of the in-phase/quadrature-phase mismatch estimation module and/or of loop weight value of at least one direct current offset correction which evolve in the time;

Fig. 8 represents an example of a table used for determining, according to an automatic gain controller headroom value, the weight values of both the phase and gain loops;

Fig. 9 exemplifies sub-period indexes and their respective durations, further to phase and gain loop weight values for in-phase/ quadrature-phase mismatch estimation module assuming an auto gain controller headroom nominal value;

Fig. 10 represents an example of an algorithm for determining weight values of the phase and gain loops applied during different time periods according to some embodiments of the invention;

Fig. 11 represents an example of an algorithm for managing the operation of the in-phase/quadrature-phase mismatch correction module and/or of the in- phase/quadrature-phase mismatch estimation module according to some embodiments of the invention;

Fig. 12 schematically represents an example of architecture of a receiving part including at least one Direct Current Offset compensation loop according to some embodiments of the invention.

Fig. 1 schematically represents an example architecture of a receiver device in which some embodiments of the present invention can be implemented.

The receiver device 10 may be included into a mobile telecommunication system, and more precisely in a radio access network (RAN), for example like in a User Equipment (for reception in the DownLink) or a Base Station (for reception in the UpLink) compatible with Long Term Evolution, Wideband Code Division Multiple Access or Global System for Mobile Communications system.

The receiver device 10 comprises the following components interconnected by a communications bus 101 : a processor, microprocessor, microcontroller or CPU {Central Processing Unit) 100 and a memory (e.g. a RAM {Random-Access Memory) 103 and/or a ROM {Read-Only Memory) 102. The receiver device 10 may also comprise an SD {Secure Digital) card reader 104 or any other device adapted to read information stored on storage means. The receiver device 10 may also comprise a wireless interface I/F 105.

The wireless interface 105 allows the receiver 10 to wirelessly communicate with a transmitter device.

CPU 100 is able of executing instructions loaded into RAM 103 from ROM 102 or from an external memory, such as an SD card. When the receiver 10 is powered on, CPU 100 reads instructions from RAM 103 and executes the read instructions. The instructions form one computer program that causes CPU 100 to perform some or all of the steps of the algorithms described hereafter with regard to Figs. 10 and 11.

Any and all steps of the algorithms described hereafter with regard to Figs. 10 and 11 may be implemented in software by execution of a set of instructions or program by a programmable computing machine, such as a PC {Personal Computer), a DSP {Digital Signal Processor) or a microcontroller; or else implemented in hardware by a machine or a dedicated component, such as an FPGA {Field- Programmable Gate Array) or an ASIC {Application-Specific Integrated Circuit).

In other words, the receiver 10 includes circuitry, or a device including circuitry, causing the receiver device to perform the steps of the algorithms described hereafter with regard to Figs. 10 and 11.

Such a device including circuitry causing the receiver 10 to perform the steps of the algorithms described hereafter with regard to Figs. 10 and 11 may be an external device connectable to the receiver 10.

The receiver 10 may also be a part of another device, for example when the receiver 10 is a chip, a chipset, or a module. Alternatively, instead of being a part of another device or connected to a dedicated communication device, the receiver 10, according to the invention, may provide communication capability to any suitable device, such as a computer device, a machine, for example a vending machine or a vehicle like a car or truck.

The term circuitry refers either to hardware implementation, consisting in analogue and/or digital processing, or to a combination of hardware and software implementation, including instructions of computer program associated with memories and processor causing the processor to perform any and all steps of the algorithm described hereafter with regard to Figs. 10 and 11.

Fig. 2 illustrates an example of the receiving part of the wireless interface of the receiver according to some embodiments of the present invention.

The receiving part of the wireless interface 105 comprises an analogue band pass filter 202 which filters signal received by an antenna 201 which is linked to the wireless interface 105 or included into the wireless interface 105.

Signals received by the antenna 201 are random signals, for example the one representative of data related to a communication with a remote telecommunication device.

The present invention is able to correct IQ mismatch without any need of known signals like the one representative of pilot symbols.

The filtered signal is amplified by a low noise amplifier 203. The gain of the low noise amplifier 203 is set by an automatic gain controller (AGC) not shown in Fig. 2.

The receiving part comprises two channels which respectively process signal provided by the low noise amplifier 203 in order to provide it to an IQ Mismatch Correction and Estimation module (IQMCE) 200 according to the invention.

A first channel is composed of a mixer 204, an analogue low-pass filter (AF) 205, a programmable analogue gain amplifier 206, an analogue-to-digital converter ADC 207, a decimator Dec 208 and a Programmable Digital Gain (PDG) 209. The first channel provides in-phase samples of the processed signal to the IQMCE module 200.

A second channel is composed of a mixer 214, an analogue low-pass filter (AF) 215, a programmable analogue gain amplifier 216, an ADC 217, a decimator Dec 218 and a PDG 219. The second channel provides quadrature-phase samples of the processed signal to the IQMCE module 200.

The global IQ mismatch can be modelled, without loss of generality, as an IQM gain error and an IQM phase error on the second mixer 214.

The output signal of the low noise amplifier 203 is converted into baseband signal in two in-phase (I) and quadrature-phase (Q) baseband components by the mixers 204 and 214.

The mixer 204, in order to provide the I baseband component of the received signal, multiplies the signal provided by the low noise amplifier 203 by cos(2nf _LO t) where fio is the local oscillator frequency of the receiver 10 and t is the time.

The mixer 214, in order to provide the Q baseband component of the received signal, multip lies the signal provided by the low noise amplifier 203 by —5g. sin(2nf _L0 . t— δφ) where 5g denotes the IQM gain error and δφ denotes the IQM phase error between the analogue components comprised in the first and second channels.

After conversion to I baseband component by the mixer 204, the I baseband component is filtered by the analogue baseband filter 205, amplified by the programmable analogue gain amplifier 206, digitally converted by the ADC 207, the digital output samples of which are decimated by the decimator 208 and the decimated samples are amplified by the PDG 209.

After conversion to Q baseband component by the mixer 214, the Q baseband component is as well filtered by the analogue baseband filter 215, amplified by the programmable analogue gain amplifier 216, digitally converted by the ADC 217, the digital output samples of which are decimated by the decimator 218 and the decimated samples are amplified by the PDG 219.

The IQMCE module 200 compensates the IQ mismatch impairment due to analogue components by performing an IQ mismatch correction and/or estimation.

According to some embodiments of the invention, the IQ mismatch correction is performed in the digital domain and more precisely on samples provided by the PDG modules 209 and 219.

Let V denote the index corresponding in the sequel to the n ^th sampled digital sample.

The correction for the IQ mismatch gain and phase impairments is performed using two real IQM correction coefficients, a and /?.

a is referred to as phase correction coefficient since its ideal value ctideai depends only on IQM phase error value δφ.

β is referred as gain correction coefficient since its ideal value β ideal depends mainly on IQM gain error value 5g.

a _ideal = tan (δφ ) The IQMCE module 200 determines the IQ mismatch phase and gain β correction coefficients values to be configured in order to compensate for overall receiver IQ mismatch. IQ mismatch estimation principle is to use an adaptive algorithm able to iteratively update the IQM phase correction coefficient a and the IQM gain correction coefficient β values in such a way that both a and β correction coefficients converge close to their respective ideal target value, that is:

a—> a ideal tan((5<p) (1)

1

β→ β ideal (2)

5g . cos((5<p)

1

Assuming (2) is verified, we get cos(<5<p)

β -Sg

or p.5g.cos(5(p)→ 1

and (1) can then be written as: a — ^■ β .<5g.sin(<5<p)

The IQ mismatch estimation algorithm hence converges if both following relationships are simultaneously fulfilled:

ε _ρ - a - /3.<5g.sin(<5<p)—· 0

ε - I - \<5g.cos(<5<p)—· 0

According to some embodiments of the invention, the IQMCE module 200 comprises a combination of two estimation loops running simultaneously and using s _g and ε _ρ as error signals, a phase estimation loop to iteratively update a correction coefficient value and a gain estimation loop to iteratively update β correction coefficient value.

The error signals s _g and ε _ρ are respectively further accumulated and weighted with a gain loop weight called K _g and a phase loop weight K _p .

The IQMCE module 200 is disclosed in reference to Fig. 3.

Fig. 3 schematically represents an example of architecture of an in- phase/quadrature-phase mismatch correction and/or estimation module according to some embodiments of the present invention.

The IQMCE module 200 comprises an in-phase/quadrature-phase Mismatch Estimation module 300 (IQME) and an in-phase/quadrature-phase Mismatch correction module 310 (IQMC).

The I samples provided by the PDG 209 are provided to the IQME module 300 and to the IQMC module 310. The Q samples provided by the PDG 219 are provided to the IQME module 300 and to the IQMC module 310.

For example, the IQMC module 310 possibly performs an IQM correction on Q samples provided by the PDG 209 based both on the I samples and the Q samples provided by the PDG 219 using correction coefficients a and β provided respectively by multiplexers 303 and 304.

It has to be noted here that with no loss of generality, the IQMC module 310 may perform the whole IQM correction on the Q samples. In a variant the IQMC module 310 may perform the IQM correction on the I samples or on I and Q samples.

The I samples provided by the PDG 209 and provided by the IQMC module 310 are noted I _ou t in Fig. 3 and the corrected Q samples are noted Q _ou t in Fig. 3. The IQMC module 310 will be disclosed more precisely in reference to Fig. 4.

The multiplexor 303 is controlled by an IQMCE DRIVE module 307 which enables the transfer of the correction coefficient determined by the IQME module 300 or the transfer of the correction coefficient stored in RAM memory 103 to the IQMC module 310. The correction coefficient stored in RAM memory 103 is a correction coefficient previously determined by the IQME module 300 and may be used when the IQME module 300 is disabled.

The multiplexor 304 is controlled by an IQMCE DRIVE module 307 which enables the transfer of the correction coefficient β determined by the IQME module 300 or the transfer of the correction coefficient β stored in RAM memory 103 to the IQMC module 310. The correction coefficient β stored in RAM memory 103 is a correction coefficient previously determined by the IQME module 300 and may be used when the IQME module 300 is disabled.

The IQME module 300 determines the correction coefficient a and provides it to the multiplexer 303. The IQME module 300 determines the correction coefficient β and provides it to the multiplexer 304. The IQME module 300 will be disclosed more precisely in reference to Fig. 5.

Fig. 4 schematically represents an example of architecture of an in- phase/quadrature-phase mismatch correction module according to some embodiments of the invention.

The Q samples provided by the PDG 219 are multiplied by the correction coefficient β by a multiplier 402 and fed to a summation module 404. The I samples provided by the PDG 209 are multiplied by the correction coefficient a by a multiplier 403 and fed to the summation module 404.

The output of the summation module 404 is linked to a multiplexor 406 which is linked to an IQMC ENABLE module 405. The IQMC ENABLE module 405 is controlled by the processor 100.

The Q samples provided by the PDG 219 are provided to the multiplexor 406. The multiplexor 406 enables the transfer of the Q corrected samples or the Q samples provided by the PDG 219 for further processing.

By such configuration, it is possible to enable or disable the operation of the IQMC module 310 independently of the IQME module 300.

For example, in some embodiments, the IQME module 300 is disabled when the reception conditions are poor. As it will be disclosed hereinafter, correction coefficients determined by the IQME module may be stored in RAM memory 103.

The processor 100 may also disable the operation of the IQMC module 310. In that case, the Q samples provided by the PDG 219 are output by the multiplexor 406.

Fig. 5 schematically represents an example of architecture of an in- phase/quadrature-phase mismatch estimation module according to some embodiments of the invention.

The IQME module 300 comprises a sample level detection module (IQME-LD) module 500 which performs on the I and Q samples provided by the PDG 209 and 219 a sample to sample selection based on the values of the r I and Q samples. The IQME- LD module 500 will be disclosed in more details in reference to Fig. 6.

The selected I and Q samples are provided to an IQM correction module (IQME-C) 501. The IQME-C module 501 performs an IQM correction as disclosed in Fig. 4. The IQME-C module 501 is a duplication of the IQMC module 310.

According to some embodiments, that duplication enables to make IQM estimation and IQM correction fully independent and possibly asynchronous. It is of particular interest for example to perform an IQM correction in the foreground using IQMC module 310 with some predefined constant a and β values that can result from a former IQM estimation loaded from RAM memory 103 whereas an IQM estimation is run in the background, using IQME module 300. Once estimation is completed, the result may be used to configure the IQMC module 310 with updated and β values. The duplication of the IQM correction within the IQME module 300 allows IQME module 300 to operate both in synchronous and asynchronous modes. For example, in the synchronous mode, the IQMC module 310 is configured with an updated set of a and β coefficients values originating from IQME module 300 for each new received I and Q samples.

For example, in the asynchronous mode, the IQMC module 310 is configured independently from IQME module 300.

The I and Q corrected samples at the output of the IQME-C module 501 are provided both to an IQM gain loop estimation constituted by the modules 502 to 508, and to an IQM phase loop estimation constituted by the modules 509 to 513.

The module 502 takes the absolute value of the I sample provided by the IQME- C module 501 and the module 503 takes the absolute value of the Q corrected sample provided by the IQME-C module 501.

A subtraction module 504 computes the IQM gain error e _g as the difference between the sample output by the module 502 and the one output by the module 503.

The IQM gain error e _g output by subtraction module 504 is then weighted by a weighting module 505, the weight of which K _g , also referred to as IQM gain loop weight value, is variable as it will be disclosed hereinafter in Figs. 7.

The IQM gain weighted error e _g output by the digital weighting module 505 is provided to an integrator 506.

For an input sample x(n) and an output sample y(n), the integrator 506 performs the following processing:

y(n) = y(n-l) + x(n), i.e. a basic accumulation or integration of the input samples.

The integrator 506 adds the current sample provided by the weighting module 505 to its internal state and outputs the integrated sample.

The absolute value of the integrated sample is taken by the module 507 and is delayed by a one sample delay noted 508 in order to obtain the IQM gain correction coefficient value β.

The coefficient value β may be transferred to the IQME-C module 501 and may also be transferred to the IQMC module 310 according to synchronous or asynchronous operation mode under use.

The multiplier 509 multiplies together I and Q selected samples provided by the IQME-C module 501. The sample resulting from the multiplier 509 is the IQM phase error ε _ρ and is weighted by a weighting module 510, the weight of which K _p , also referred to as IQM phase loop weight value, is variable as it will be disclosed hereinafter in Fig. 7.

The sample output by the weighting module 510 is provided to an integrator 51 1. The integrator 51 1 adds the current sample provided by the weighting module 510 to its internal state and outputs the integrated sample, the IQM phase integrated weighted error signal.

The integrator 511 is identical to the integrator 506.

The sign of the integrated sample is changed by the multiplier 512 which multiplies the integrated sample by minus one. The sample provided by the multiplier 512 is delayed by a one sample delay noted 513 in order to obtain the IQM phase correction coefficient value a.

The coefficient value a is transferred to the IQME-C module 501 and may also be transferred to the IQMC module 310 according to synchronous or asynchronous operation mode under use.

It has to be noted here that, the loop constituted by the modules 502 to 508 and/or the loop constituted by the modules 509 to 513 may be used for other purposes than IQM estimation. For example, the loop constituted by the modules 502 to 508 may be used for Direct Current (DC) offset estimation. A more detailed example is given in reference to Fig. 12. The weight values used by the weighting modules 505 and 506 may also be variable within different sub-period durations in a same manner as the ones that will be disclosed hereinafter in Figs. 7. The weight values used by the weighting modules 505 and 510 during the sub-periods may also be defined in a same manner as the ones that will be disclosed hereinafter in Figs. 8 and/or 9.

Fig. 6 schematically represents an architecture of a sample level detection module according to some embodiments of the invention.

The sample level detection module (IQME-LD) 500 comprises two absolute value modules 600 and 610.

The module 600 takes the absolute value of the I sample provided by the PDG 209 and the module 610 takes the absolute value of the Q sample provided by the PDG 219.

The samples output by the modules 600 and 610 are provided to a maximum detection module (MAX) 601 which selects the maximum among the two samples provided by the modules 600 and 610. The selected sample is fed to two comparison modules 603 and 605.

The comparison module 603 compares the selected sample to an high threshold value A max and if the selected sample is greater than the high threshold value A max, the comparison module 603 outputs a binary value one.

The comparison module 605 compares the selected sample to a low threshold value A min, and if the selected sample is less than the low threshold A min, the comparison module 605 outputs a binary value one.

The high threshold value A max and the low threshold A min value are stored in dedicated registers and may be modified anytime.

The binary values provided by the comparison modules 603 and 605 are fed to an OR gate 606, the output of which commands two multiplexors 607 and 608.

The I samples provided by the PDG 209 are provided to the multiplexor 607 and the Q samples provided by the PDG 219 are provided to the multiplexor 608.

When the output level of the OR gate 606 is equal to one, the multiplexor 607 enables the transfer of the I sample provided by the PDG 209 and the multiplexor 608 enables the transfer of the Q sample provided by the PDG 219.

When the output level of the OR gate 606 is equal to null value, the multiplexors 607 and 608 do not provide any sample since its value is considered as not reliable for further processing.

Thanks to the IQME-LD module 500, it is possible to reject samples having too low amplitude or too high amplitude. Such samples may delay the convergence of the gain and phase estimation loops of the IQME module 300.

Figs. 7a and 7b schematically represent some examples of loops weight values of the in-phase/quadrature-phase mismatch estimation module and/or of at least one loop weight value of a direct current offset correction which evolve in the time.

Fig. 7a schematically represents some examples of phase loop weight values of the IQME module 300 which evolve in the time.

Fig. 7b schematically represents some examples of gain loop weight values of the IQME module 300 which evolve in the time.

According to some embodiments of the invention, the weight value K _p respectively K _g of the phase respectively gain loop of the IQME module 300 evolves in the time.

K _p and K _g values are modified several times during the whole estimation duration. The time duration during which the loop weight value is kept constant is referred to as sub-period. Thereby, the whole estimation is split into a series of successive sub-periods.

According to some embodiments of the invention, each sub-period may have a specific duration. For example, the sub-period duration may follow a geometrical series with a factor Fl equal to either 1 , 2, 4 or 8. A given sub-period of specific duration D is followed by a next sub-period whose duration is Fl times longer.

In the same way, the loop weight values (K _p and Kg) for both IQM estimation loops also follow a geometrical series with a factor F2 lower than one. For example F2 is equal to 0.5 or 0.25. A given sub-period applying a couple {K _p , K _g } as loop weight values is followed by a next sub-period for which the loop weight values [K _p . F2, K _g . F2 are— times lower.

Furthermore, the loop weight values K _p and K _g depend on an AGC headroom parameter. The AGC controls at least the gain of the low-noise amplifier 203, the programmable analogue gain amplifiers 206 and 216 and the PDG 209 and 219.

AGC headroom parameter value is a common way to express the digital signal level value referred to ADC full scale level. AGC headroom parameter is defined as the difference in decibels (dB) between ADC full scale level expressed in dB and the targeted signal level at the output of the ADC expressed in dB.

AGC headroom value is a strictly positive value expressed in dB. For example, the AGC headroom is typically equal to 15 dB.

In the examples given in Figs. 7a and 7b, the IQM estimation total available time duration referred to as D _tot is divided into five sub-periods. It has to be noted the number of sub-periods may be lower or greater than five. The first sub-period 70 has a first duration, the second sub-period 71 has a second duration which is four times the first duration, the third sub-period 72 has a third duration which is four times the second duration, the fourth sub-period has a duration which is equal to four times the third sub duration and the fifth sub-period 74 has a duration which is four times the fourth duration and is equal to ¾ of D _tot .

In the examples given in Figs. 7a and 7b, the IQM estimation weight values K _p o for phase loop, K _g0 for gain loop during the first sub-period 70 is equal to a predetermined value dependent on the AGC headroom value. The weight value K _p i, respectively K _g i, during the second sub-period 71 is equal to half the weight value K _p0 respectively K _g0 . The weight value K _p2 , respectively K _g2 , during the third sub-period 72 is equal to half the weight value K _p i, respectively K _g i . The weight value K _p3i respectively K _g3 , during the fourth sub-period (not shown in Fig. 7a) is equal to half the weight value K _p2 , respectively K _g2 . The weight value K _p4i respectively K _g4 , during the fifth sub-period 74 is equal to half the weight value K _p3i respectively K _g3 .

Let M _p holding for IQM phase estimation loop and M _g for IQM gain estimation loop denote the product of the last, the fifth in the example of Figs. 7a and 7b, sub- period duration by the loop weight value K _p4 respectively K _g4 used during said last fifth sub-period.

The product of the fourth sub-period duration by the loop weight value K _p3 used during said fourth sub-period is equal to M _p /2. The product of the third sub-period duration by the loop weight value K _p2 used during said third sub-period is equal to M _p /4. The product of the second sub-period duration by the weight value K _p i used during said second sub-period of time is equal to M _p /8. The product of the first sub- period duration by the weight value K _p0 used during said first sub-period of time is equal to M _p /16.

The product of the fourth sub-period duration by the loop weight value K _g3 used during said fourth sub-period is equal to M _g /2. The product of the third sub-period duration by the loop weight value K _g2 used during said third sub-period is equal to M _g /4. The product of the second sub-period duration by the weight value K _g i used during said second sub-period of time is equal to M _g /8. The product of the first sub- period duration by the weight value K _g0 used during said first sub-period of time is equal to M _g /16.

According to some embodiments of the invention, at least one weight value IQ of a DC offset correction loop which will be disclosed hereinafter in reference to Fig. 12 evolves in the time. For example, the weight value ¾ of a DC offset correction loop for the channel providing I sample. Another weight value of a DC offset correction loop for the channel providing Q samples.

K _d value is modified several times during the whole estimation duration. The time duration during which the DC offset weight value is kept constant is referred to as sub-period. Thereby, the whole estimation is split into a series of successive sub- periods.

According to some embodiments of the invention, each sub-period may have a specific duration. For example, the sub-period duration may follow a geometrical series with a factor Fl equal to either 1, 2, 4 or 8. A given sub-period of specific duration D is followed by a next sub-period whose duration is Fl times longer. In the same way, the weight values Kd also follows a geometrical series with a factor F2 lower than one. For example F2 is equal to 0.5 or 0.25. A given sub-period applying Kd as loop weight value is followed by a next sub-period for which the loop weight values {K _d . F2 } are— times lower.

F 2

In the examples given in Figs. 7a and 7b, the DC offset estimation total available time duration referred to as D _tot is divided into five sub-periods as already disclosed. It has to be noted that the number of sub-periods may be lower or greater than five. The first sub-period 70 has a first duration, the second sub-period 71 has a second duration which is four times the first duration, the third sub-period 72 has a third duration which is four times the second duration, the fourth sub-period has a duration which is equal to four times the third sub duration and the fifth sub-period 74 has a duration which is four times the fourth duration and is equal to ¾ of D _tot .

In the present examples, the weight value K _d i during the second sub-period 71 is equal to half the weight value K _d o- The weight value K _d2 , during the third sub-period 72 is equal to half the weight value K _d i - The weight value K<B, during the fourth sub- period is equal to half the weight value Ka ₂ . The weight value K _d4 , during the fifth sub-period 74, is equal to half the weight value IQ ₃ .

Let M _p holding for IQM phase estimation loop and M _g for IQM gain estimation loop denote the product of the last, the fifth in the example of Figs. 7a and 7b, sub- period duration by the loop weight value K _p4 respectively K _g4 used during said last fifth sub-period.

The product of the fourth sub-period duration by the loop weight value K 3 used during said fourth sub-period is equal to M _d /2. The product of the third sub-period duration by the loop weight value IQ2 used during said third sub-period is equal to M _d /4. The product of the second sub-period duration by the weight value K _d i used during said second sub-period of time is equal to M _d /8. The product of the first sub- period duration by the weight value K _d o used during said first sub-period of time is equal to M _d /16.

Fig. 8 represents an example of a table used for determining, according to an automatic gain controller headroom value, the weight values of both the phase and gain loops.

Fig. 8 consists in a table containing M _p and M _g example values according to the AGC headroom parameter value. M _p and M _g values enable to derive the series of suitable loop weight values for both IQM phase and gain estimation loops, as well as the convenient application duration for each of them, knowing from the whole IQM estimation duration selected value (D _tot ) and from the selected number of sub-periods. The table shown in Fig. 8 is, for example, stored in the RAM memory 103.

The column noted 80 shows different possible values expressed in dB that the AGC headroom value can take.

For a given AGC headroom value given in column 80, the column 81 , respectively 82, indicates the recommended M _p , respectively M _g value to be used.

The period of time D _tot is equal to a predetermined value for example stored in RAM memory 103, the different successive loop weight values like K _p0 to K _p4 , K _g0 to K _g4 shown in Figs. 7a and 7b can be deduced respectively from M _p and M _g .

Fig. 9 exemplifies sub-period indexes and their respective durations, further to phase and gain loop values for in-phase/quadrature-phase mismatch estimation module assuming an auto gain controller headroom nominal value.

The table shown in Fig. 9 is, for example, stored in the RAM memory 103.

The AGC headroom nominal value is, for example, equal to 15dB.

The line noted 90 shows the series of successive sub-period indexes.

The line noted 91 shows the series of successive sub-period time duration, expressed in number of samples.

The line noted 92 respectively. 93 shows the series of loop weight values K _p , respectively K _g for IQM phase respectively gain estimation loop.

Fig. 10 represents an example of an algorithm for determining weight values of the phase and gain loops applied during different time periods according to some embodiments of the invention.

The present algorithm may be executed by the CPU 100 of the receiver 10. The present algorithm will be disclosed in an example and in a non limitative way, wherein it is executed by the processor 100.

At step S I 00, the CPU 100 checks if any condition regarding the analogue part of the receiving chain has changed.

Condition change may be a modification of any analogue gain among the low noise amplifier 203, the programmable analogue gain amplifier 206 or 216, or the programmable digital gain 207 or 219 and/or of a change of the frequency band in which radio signals are received.

If any condition regarding the analogue part of the receiving chain changes, the CPU 100 moves to step S 101. Otherwise, the CPU 100 moves to step S I 06. At step S101, CPU 100 stores the context of the IQME module 300 in the RAM memory 103. The context of the IQME module 300 is, for example, the current state of the integrator 511, the current state of the integrator 506, the current index of the sub-period and one bit value which indicates if the current context has already been used or not. The context is further associated with the values of the different gains of the low noise amplifier 203, of the programmable analogue gain amplifiers 206 and 216, of the programmable digital gains 207 and 217 and/or the frequency band in which radio signals are received prior the change of conditions detected at step SI 00.

The memory 103 stores the contexts for the different supported analogue gain combinations and/or the frequency band in which radio signals are received.

At next step SI 02, it is checked if there is, in the memory 103, a context which corresponds to the combination of gains and/or the frequency band used once the condition change is detected.

If there is a context which corresponds to the combination of gains and/or the frequency band in which radio signals are received used once the condition change is detected, the CPU 100 moves to step SI 05. Otherwise, the CPU 100 moves to step S103.

At step SI 05, the CPU read in the RAM memory 103 the context which corresponds to the combination of gains and/or the frequency band in which radio signals are received once the condition change is detected and sets the state of the integrator 511 to the value stored in the context, the state of the integrator 506 to the value stored in the context, applies the loop weights K _p and K _g which correspond to the index of the sub-period index stored in the context.

After that, the CPU 100 moves to step SI 06.

At step SI 03, the CPU 100 determines, using the table shown in Fig. 9 and the knowledge of the AGC headroom value, the values M _p and M _g .

At next step S I 04, the CPU 100 determines, using the values M _p and M _g , the values of K _p0 to K _p4 and K _g0 to K _g4 .

At next step SI 06, the CPU 100 starts a sub-period of time. If CPU 100 was previously at step SI 05, the sub-period to fully replay is the one which corresponds to the index of sub-period stored in the context read from the memory 103.

If CPU 100 was previously at step SI 00, the sub-period of time which corresponds to the following index of sub-period of time as the previous one index is incremented since a new sub-period is started. If CPU 100 was previously at step SI 04, the sub-period is the first sub-period.

At next step SI 07, the CPU 100, when the following sub-period has to start, applies the values of K _p and K _g which correspond to the next sub-period.

At next step SI 08, the CPU 100 checks that all sub-periods have been successively performed.

If all the sub-periods have been performed, the CPU 100 moves to step SI 09. Otherwise, the CPU moves to step SI 00.

At step SI 09, the CPU 100 stores, in RAM memory 103, the context of the IQME module 300. The context of the IQME module 300 is for example the current state of the integrator 511, the current state of the integrator 506, the current sub- period index and one bit value which indicates if the context has already been used or not. The context is further associated with the values of the different gains of the analogue low noise amplifier 203, of the programmable analogue gain amplifiers 206 and 216, of the programmable digital gains 207 and 217 and/or the frequency band in which radio signals are received prior the change of conditions detected at step SI 00.

In some embodiments, one bit value which indicates if the context has already been used or not avoids glitch in the quality of the received radio signal when both IQM estimation and correction are enabled in synchronous mode.

In some embodiments, when a given analog context is visited for the first time, this information is available thanks to the one-bit value, integrator 506 and 51 1 states are not reset with some prescribed values but advantageously initialized with the most likely values copied from another context for which IQM estimation has already started for a certain and as long as possible, amount of time.

After that, the CPU 100 returns to step SI 00.

Fig. 11 represents an example of an algorithm for managing the operation of the in-phase/quadrature-phase mismatch correction module and/or of the in- phase/quadrature-phase mismatch estimation module according to some embodiments of the invention.

The present algorithm may be executed by the CPU 100 of the receiver 10. The present algorithm will be disclosed in an example and in a non limitative way, wherein it is executed by the processor 100.

At step SI 10, the CPU 100 checks if the IQMC module 310 and the IQME module 300 need to be activated. If the IQMC module 310 and the IQME module 300 need to be activated, the CPU 100 moves to step SI 11. Otherwise, the CPU 100 moves to step SI 13.

At step Si l l, the CPU 100 activates the IQMC module 310 and the IQME module 300.

At next step SI 12, the CPU 100 commands the IQMCE DRIVE module 307 which enables the transfer of the correction coefficients a and β determined by the IQME module 300 to the IQMC module 310.

After that, the CPU returns to step SI 10.

At step SI 13, the CPU 100 checks if the IQME module 300 needs to be activated.

If the IQME module 300 needs to be activated, the CPU 100 moves to step SI 14. Otherwise, the CPU 100 maintains or sets the IQME module 300 in a deactivated mode and moves to step SI 18.

At step SI 14, the CPU activates the IQME module 300.

At step SI 15, the CPU 100 checks if the IQMC module 310 needs to be activated.

If the IQMC module 310 needs to be activated, the CPU 100 moves to step SI 16. Otherwise, the CPU 100 maintains or sets the IQMC module 310 in a deactivated mode and moves to step SI 17.

At step SI 16, the CPU 100 commands the IQMCE DRIVE module 307 which enables the transfer of the correction coefficients a and β determined by the IQME module 300 to the IQMC module 310.

After that, the CPU 100 returns to step SI 10.

At step SI 17, the different correction coefficients or contexts determined by the IQME module 300 may be stored in the RAM memory 103.

After that, the CPU 100 returns to step SI 10.

At step SI 18, the CPU 100 checks if the IQMC module 310 needs to be activated.

If the IQMC module 310 needs to be activated, the CPU 100 moves to step SI 19. Otherwise, the CPU 100 maintains or sets the IQMC module 310 in a deactivated mode and moves to step SI 10.

At step SI 19, the CPU 100 commands the IQMCE DRIVE module 307 which enables the transfer of the correction coefficients a and β stored in the RAM memory 103 to the IQMC module 310. After that, the CPU 100 returns to step S I 10.

Fig. 12 schematically represents an example of architecture of a receiving part including Direct Current Offset compensation loop according to some embodiments of the invention.

The receiving part of the wireless interface 105 comprises an analogue band pass filter 1202 which filters signal received by an antenna 1201 which is linked to the wireless interface 105 or included into the wireless interface 105.

The filtered signal is amplified by a low noise amplifier 1203. The gain of the low noise amplifier 1203 is set by an automatic gain controller (AGC) not shown in Fig. 12.

The output signal of the low noise amplifier 1203 is converted into baseband signal by a mixer 1204 for a channel providing I samples, the channel providing I samples being composed of subtracting means 1205, an analogue baseband filter 1206, a programmable analogue gain amplifier 1207, an analogue to digital converter (ADC) 1208, a decimator 1209 and a programmable digital gain (PDG) 1210.

It has to be noted here that the output signal of the low noise amplifier 1203 is converted into baseband signal by at a mixer 1214 witch multiplies signal provided by the low noise amplifier 1203 by—sin(2nf _LO t) for a channel providing Q samples, not shown in Fig. 12. The channel providing Q may be identical to the channel providing I samples.

The mixer 1204, in order to provide the baseband signal of the received signal, multiplies the signal provided by the low noise amplifier 1203 by cos(2nf _LO t) whereio is the local oscillator frequency of the receiver 10 and t is the time.

After conversion to baseband signal by the mixer 1204, a DC correction value determined according to the present invention is subtracted to the base band signal by subtraction means 1205. The signal provided by the subtraction means is filtered by the analogue baseband filter 1206, amplified by the programmable analogue gain amplifier 1207, digitally converted by the ADC 1208, the digital output samples of which are decimated by the decimator 1209 and the decimated samples are amplified by the (PDG) 1210.

The samples provided by the PGD 1210 are provided to circuitry, not shown in Fig. 12, for further processing and provided to a weighting module 121 1 , the weight of which Ka, also referred to as DC Offset loop weight value, is variable as it has been disclosed in Figs. 7. The output of the digital weighting module 121 1 is provided to an integrator

1212.

For an input sample x(n) and an output sample y(n), the integrator 1212 performs the following processing:

y(n) = y(n-l) + x(n), i.e. a basic accumulation or integration of the input samples.

The integrator 1212 adds the current sample provided by the weighting module 1211 to its internal state and outputs the integrated sample.

The integrated sample is provided to the subtraction means 1205.