METHOD FOR ESTIMATING DEPTH OF LATENT SCRATCHES IN SiC SUBSTRATES

Title:

METHOD FOR ESTIMATING DEPTH OF LATENT SCRATCHES IN SiC SUBSTRATES

Document Type and Number:

WIPO Patent Application WO/2015/151411

Kind Code:

A1

Abstract:

This method for estimating the depth of latent scratches in SiC substrates includes an etching step, a measurement step, and an estimation step. In the etching step, a SiC substrate in which at least the surface is formed from single-crystal SiC, and which has been subjected to machining, is subjected to heat treatment under an Si atmosphere to etch the surface of the SiC substrate. In the measurement step, the surface roughness or the residual stress of the SiC substrate which has been subjected to the etching step is measured. In the estimation step, the presence or depth of latent scratches in the SiC substrate prior to the etching step is estimated on the basis of the results obtained in the measurement step.

Inventors:

TORIMI SATOSHI (JP)
YABUKI NORIHITO (JP)
NOGAMI SATORU (JP)

Application Number:

PCT/JP2015/001301

Publication Date:

October 08, 2015

Filing Date:

March 10, 2015

Export Citation:

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Assignee:

TOYO TANSO CO (JP)

International Classes:

H01L21/66

Foreign References:

JP2011009661A	2011-01-13
JP2003234313A	2003-08-22
JP2012049392A	2012-03-08

Other References: