For example, in an SVGA Field Emission Display, there are 800 columns, each column composed of 3 sub-columns (Red, Green and Blue) and 600 rows or lines. Each row requires a simple ON or OFF driver, essentially a two level driver, and there are 600 drivers required per display. Each sub-column, however, requires a gray scale driver that may be required to provide 256 or more different levels of brightness, and there are one gray scale driver required per each sub-pixel or 800 x 3 = 2,400 of these drivers required per display.

Thus, if the row and column drivers cost exactly the same, there would still be a 4: 1 ratio of costs due simply to the number of drivers. However gray scale drivers are actually much more expensive than simple two-level drivers since they contain significantly more circuitry and therefore the additional cost would be much greater than 4: 1.

There are two methods of generating the differing levels of pixel brightness in a gray scale driver. The first method is to vary the output voltage or output current provided by the driver. The higher the voltage or current, the brighter the pixel brightness. However, when the brightness is less than maximum, the excess energy that does not go to lighting the pixel is dissipated across the driver, generating heat. This makes the driver expensive because it must dissipate this heat in order to properly operate and few drivers can be packed in one chip because of this heat problem. It is also very complicated and expensive to build a driver, which translates digital picture information into the varying output voltages or currents needed for gray scale. Additionally, when the pixel is driven at a low brightness level with reduced voltage or current, the pixel may not be driven at its full efficiency, causing reduced display efficiency and uneven pixel illumination and sharpness.

The second method overcomes these heat and efficiency problems by utilizing the fact that the human eye cannot perceive fast changes in brightness and therefore integrates, or averages, the total light received over time and"sees"an average brightness. In this method, known as Pulse-Width Modulation, the pixel is driven at maximum brightness for a certain period of time and then turned off for another period of time. Because the driver circuit is only fully on or fully off, a minimum amount of the energy is lost in the driver and the pixel is

always on at full efficiency. By varying the portion of a cycle that the pixel is lit, the perceived brightness can be varied from barely on to fully on.

However, the circuits to accomplish this second method of gray scale are very complicated. As can be seen in FIGURE 1A, a typical gray scale circuit includes a latch or shift register to store the binary gray scale number before it is used, a latch to store the active gray scale number, a counter to generate the time slots, a comparator circuit to determine if the counted number is less than, equal to or greater than the stored gray scale number, and a driver transistor.

In the operation of the circuit shown in FIGURE 1A, the binary gray scale number is first stored in the latch or shift register for later transfer to the active latch. After the data is transferred to the active latch, the counter is reset to zero and then begins counting up to a maximum number, which defines one complete brightness cycle, defined as T in FIGURE 1B. Each time the counter counts up, its output is compared by the comparator circuit with the gray scale number stored in the active latch. If the stored number in the active latch is lower than the count number from the counter, the comparator circuit will set the driver transistor to ON. When the gray scale number becomes equal to or greater than the count from the counter, the comparator circuit turns the driver transistor to OFF. The period of time when the driver is ON is shown as X in FIGURE 1B. The overall brightness of the pixel in the typical gray scale circuit described in FIGURE 1A is defined by the ratio of X to T shown in FIGURE 1B, where X is defined as the time the driver is ON and T is defined as the total time period for one complete brightness cycle. This solution requires a large amount of circuitry to drive a pixel according to gray scale.

Therefore, there exists a need to reduce the amount of gray scale circuitry to drive a pixel for various types of flat panel displays.

SUMMARY OF THE INVENTION The present invention provides a programmable pulse width modulation generator circuit for generating a pulse width modulated signal with a variable duty cycle. The generator circuit includes a data loading circuit for receiving a data word representing the desired duty cycle of the pulse width modulated signal to be generated. The data word comprises a plurality of data bits, each bit having at least one of a selected or unselected state.

The generator circuit also includes a generating circuit coupled to data loading circuit for receiving a plurality of periodic pulse width modulated signals, and for generating a pulse width modulated signal by combining each constituent pulse width modulated signals that correspond to a data bit in the data word that indicates the selected state.

In accordance with other aspects of the present invention, each constituent pulse width modulated signal has an ON portion that is unique during a common period shared by the constituent pulse width modulated signals. The ON portion of each constituent pulse width modulated signal is binary weighted so that the ON portion of each of the constituent pulse width modulated signals is related by a unique power of 2 to the ON portion of each other of the constituent pulse width signals.

In the present embodiment, the ON portions of the constituent pulse width modulated signals are ordered in time according to their binary weight, although in other embodiments the constituent pulse width modulated signals may occur in any order as long as no two pulse width modulated signal's ON portions overlap in time, each pulse width modulated signal's ON portion begins as the prior pulse width modulated signal's ON period turns OFF and all pulse width modulated signals together shall constitute one complete common or brightness period.

In the present embodiment, the constituent pulse width modulated signal having the ON portion with the greatest magnitude occurs at the end of the common period, although in other embodiments each pulse width modulated signal may occur at any location in the common or brightness period.

In an alternate embodiment the circuit includes a clock that generates a clock signal having a plurality of clock pulses, the clock pulses being spaced by weighted intervals during a signal period and a register for receiving a data word with a plurality of data bits, and that generates a pulse width modulated signal by comparing each data bit to a corresponding one of the clock pulses.

Each data bit is at least one of a selected or unselected state, and the pulse width modulated signal has an ON portion during the length of time of the clock pulses that when compared has corresponding data bit in the selected state.

In accordance with other aspects of the present invention, the register includes a plurality data latch circuits that shift the data bits through each of the plurality of data latch circuits to a following data latch circuit in accordance with the plurality of clock pulses.

The preferred embodiment of the alternate embodiment of the present invention includes binary weighting the intervals of the clock pulses.

The preferred embodiment of the alternate embodiment of the present invention also includes a latch circuit that latches in a portion of a next data word for a next signal period in the register during at least one of the clock pulses in the present signal period.

In the preferred embodiment of the alternate embodiment of the present invention, the data word represents a gray scale value and a driver circuit that drives a display element according to the generated pulse width modulated signal.

As will be readily appreciated from the foregoing summary, the invention provides an improved-circuit for generating a pulse width modulated signal for sending gray scale information to a display.

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: FIGURES 1A and B illustrate gray scale circuitry and timing as performed by the prior art; FIGURE 2 is a flow diagram of the method of the present invention; FIGURE 3 is graph of a set of reference input signals used in the present invention; FIGURES 4A and B are a graph illustration of selected reference input signals and a resulting pulse width modulation signal; FIGURE 5 is a diagram illustrating the present invention; FIGURE 6 is an example circuit diagram for implementing the logic diagram of FIGURE 5; FIGURES 7A and B is graph of a set of reference input signals; FIGURES 8A and B are example diagrams illustrating examples of the present invention; and FIGURE 9 is a flow diagram of the present invention; FIGURES 10 and 11 are diagrams of example clock signals used in the present invention; FIGURE 12 is an example circuit diagram of the present invention; FIGURE 13 is an example of the present invention used with the circuit illustrated in FIGURE 12; FIGURE 14 is a circuit diagram of an alternate embodiment of the present invention; FIGURE 15 is an example of the present invention used with the circuit illustrated in FIGURE 14; and FIGURE 16 is an illustration of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The methods and circuits of the present invention provide a programmable Pulse Width Modulated ("PWM") signal generator using considerably fewer gates than are presently required using the prior art methods described above.

In overview, the present invention comprises a programmable generation circuit to which a plurality of constituent PWM signals are input. When programmed with a data word that represents a desired duty cycle for the PWM signal to be output, the programmable generation circuit selects the appropriate constituent PWM signal (s) and adds them together to generate a composite output PWM signal. Because many programmable generation circuits can share the same constituent PWM signal inputs, considerably less circuitry is required to generate many output PWM signals than would be required using prior art methods.

A method of the present invention is illustrated in FIGURE 2. The method begins by generating a set of S signals, see block 210. Although there are alternative configurations discussed below, most often the S signals will be pulse width modulated signals that each contain a single pulse that has a unique duration and period during a total period referred to as an S-cycle. A data word is received at block 220. The data word indicates a desired duty cycle for a pulse width modulated signal that will be used to drive a load, such as a pixel driver. At block 230, the data word is used to select a subset of constituent S signals from the set of S signals generated in block 210. The selected subset of constituent S signals are combined at block 240 into a composite S signal. The composite S signal is output to a load at block 250. From the perspective of the load, which averages the pulses over time, the S signal appears as a pulse width modulated signal with a duty cycle approximately equal to the duty cycle called for in the data word.

An exemplary composition of the constituent PWM signals ("S signals") is illustrated in FIGURE 3. These S signals may be advantageously used in digital computer systems, as the binary weighting of S signals particularly support this application. The weighting of the S signals can be performed various other ways while remaining within the scope and spirit of the invention.

In FIGURE 3, each of the S signals 310a-g has a period which occurs during T 312.

At particular times during the period T 312, a pulse 316a-g is generated. The number (n) of S signals is theoretically unlimited, but is decided by the resolution requirements for controlling the duty cycle of the output PWM signal and is practically constrained by the space available for a transmission bus to couple the S signals to the programmable generation circuits. Each pulse 316a-g has its own unique place in time 318a-g during the period T 312.

For example, in FIGURE 3, S signal So 310a occurs at time period So-I/T 318a, at the

beginning of the T period, S signal Si 310b occurs at time period Sl-l/T 318b, immediately after S signal So goes LOW, S signal S2 310c occurs at time period S2-1/T 318c, immediately after S signal S1 goes LOW, S signal S3 310d occurs at time period S3-1/T 318d, immediately after S signal S2 goes LOW, S signal S4 310e occurs at time period S4-1/T 318e, immediately after S signal S3 goes LOW, S signal Ss 310e occurs at time period Ss-1/T 318e, immediately after S signal S4 goes LOW, and so on, until the last two S signals in the series are positioned with S signal Sn-2 310f occurring at time period Sn 2-1/T 318f,, immediately after S signal Son 3 goes LOW and S signal Sn l 310g occurring at time period Sn l-1/T 318g, immediately after S signal Sn2 goes LOW. The pulses 316a-g do not require sequential placement as just described, but may be reordered in any pattern desired.

Power in a PWM signal is transmitted through the ON pulse length, which is averaged by the load over the total period (T) of the signal. The shape of a PWM signal 510 generated by the prior art for the given programmed value 01010 is illustrated in FIGURE 4A and a functionally equivalent PWM signal 512 generated by the present invention is illustrated in FIGURE 4B. The exemplary PWM signals in FIGURES 4A and 4B reflect a duty cycle specified in an exemplary 5-bit data word 514 and 516. In FIGURE 4A, the data word represents a binary value of 01010 or decimal 10. Since the data word is 5 bits, the cycle time (l) for the PWM signal 510 is defined as T = 2n, where n = the number of bits in the data word. Since the data word is 5 bits, T would be 25 or 32 periods. The value in the data word reflects that the PWM should have a duty cycle of 10/32T, which is generated by the prior art in the manner described above, as a single pulse 520 with a duration of 10 periods. The power delivered by this pulse 520 is the cycle time T divided by the length of time that the pulse is ON or 10/32T.

Instead of providing the circuitry at each PWM generator to generate a single pulse 520 with a programmed duration, the present invention employs a generation circuit to combine zero or more S signals into a PWM signal 512 with a desired total duty cycle. The S signals are generated elsewhere and contain pulses with known characteristics. For example, in FIGURE 4B the data word 516 has a binary value of 01010 or decimal 10 522 whose positions are associated with S signals Si 526 and S3 528. S signal S 1526 has a pulse 530a with a period of 2 (21) and S3 528 has a pulse 532a with a period of 8 (23). When constituent S signals Si 526 and S3 528 are combined by the generation circuit, the PWM signal 512 results and contains a pulse 530b with a period of 2 (21) and a pulse 532b with a period of 8 (23). Since the power transmitted by the pulses 530b and 532b is averaged by the load, the total power transmitted by the PWM signal 512 in this example is defined as S"""'/T, where St'al is defined as the total S periods ON and T is defined as T = (2"-1), where n = the total

number of S signals. In the example shown in FIGURE 4B, T would be (25-1) or 31 periods since there are 5 S signals and St°tal would be Sl pulse 530b with a period of 2 (2) and S3 pulse 532b with a period of 8 (23) or 10 periods. The total power transmitted by the PWM signal 512 would therefore be 2+8/31T or 10/31T. PWM signal 510 and PWM signal 512, therefore, have a functionally equivalent duty cycle.

It should be noted that in the present invention the total T cycle time is always one period less than the T cycle time in the prior art for the same given number of bits, causing a slight difference in the power delivered by the present invention for the same data word. For example, in a 5 bit system T would equal 32 periods in the prior art and 31 periods in the present invention. For an 8 bit system, T would equal 256 periods in the prior art and 255 periods in the present invention. This occurs because the counter circuit used to count the T cycle time in the prior art starts its cycle with a count of 0 for one period, while the present invention does not utilize a counter and begins its cycle with period 1, bypassing period 0.

This small difference in number of periods in T between the prior art and the present invention is not noticeable to the human eye and would represent a difference of only 0.2% in power delivered in an 8 bit system between the prior art and the present invention.

In very low bit systems, where this difference may become noticeable and compatibility with the prior art is required, a single blank period in which no S signals are ON can be added to the T cycle to compensate.

The bits in the data word do not have to be in binary format and any coding pattern can be accommodated by the present invention by associating bit positions with S signals. In the example shown in FIGURE 4B it is assumed that the data word is presented in binary format, and as such, since the data word is 5 bits, a cycle time (T) for the PWM signal 512 is divided into (25-1) or 31 periods. The value in the data word reflects that the PWM should have a duty cycle of 10/31T.

The data word need not be ordered in any particular manner. The positions of the bits are mapped by bit assignment to the S signals. The present invention can accommodate any number of states for the bit values. The order that pulses appear in S cycle and the duration of the pulses need not be in a sequential or weighted format.

A generation circuit 910 is illustrated in block form in FIGURE 5. The generation circuit comprises an n-bit data latch 912 which receives data 914 from a parallel data bus 916 or via a serial data line 918. When the n-bit data latch 912 receives serial data, it may be implemented as a serial to parallel shift register or a series of D flip-flops coupled in an equivalent manner. The data latch may be omitted when data is present on the parallel data bus 916 for a period that exceeds the S cycle (e. g., 312, FIGURE 3, above). The n-bit data

latch 912 may have any number"n"latches available, but generally n will equal the size of the data word used to program the generation circuit 910 for a duty cycle with the appropriate resolution. (Extra latches are used advantageously in an actual embodiment of the invention for controlling grayscale, described in detail below).

The data latch 912 is coupled to a first input 920a-f of a plurality of two input AND gates 922a-f. There is a two input AND gate 922a-f for each bit n in the data word. A second input 924a-f of the AND gates 922a-f are respectively coupled to S signal generators 926a-f (FIGURE 5), generally through a bus arrangement 928a-f that supplies their respective S signals (FIGURE 3) to many generation circuits 910 that each drive their own load 930 with a programmable PWM signal directly or through intermediate circuitry such as a power driver 940. An output 932a-f of each respective AND gate 922a-f is coupled to an n input 934a-f (or equivalent) OR gate 936. The OR gate may be implemented as a"wired-OR"to save circuitry, below. An output 938 of the OR gate 936 is coupled to the load 930 or intermediate circuitry such as a power driver 940.

An example electronic circuit 1010 incorporating the present invention is illustrated in FIGURE 6. A plurality of data latch circuits 1012a and 1012b receive and store data D1 1014a-Dn 1014b from a data bus (not shown). The data latch circuits 1012a and 1012b are coupled to a generation circuit 1016. The generation circuit is also coupled to S Signal Bus 1020. Based on the individual states of the data latch circuits 1012a and 1012b, the generation circuit selects a corresponding zero or more corresponding S signals 1022a and 1022b, sums those S signals 1022a and 1022b, and couples the resulting summed S signal to a driver circuit 1024. A load 1026, such as a phosphor pixel, is connected to the driver circuit 1024.

In more detail, each latch circuit 1012a-b comprises a data input 1014a-b coupled to a drain 1030a-bof a transistor 1032a-b. The source 1030a-b is also coupled to a gate 1034a-b of a transistor 1036a-b. The source 1038a-b of the transistor 1036a-b is connected to a supply voltage (Vdd). The drain 1040a-b of the transistor 1036a-b is coupled to a gate 1042a-b of transistor 1032a-b and a resistor 1044a-b. A drain 1028a-b of the transistor 1032a-b is coupled to a resistor 1046a-b. The resistors 1044a-b and 1046a-b are also connected to ground. The transistors 1032a-b and 1036a-b latch the state of the data 1014a-b. While generally there will be a data latch circuit 1014a-b for each data bit in a data word, the present invention may have any number of data latch circuits. For example, additional data latch circuits may precede or supplement data latch ciruitslO14a-b when pre-loading data is desirable.

An output 1046a-b from each data latch circuits 1012a-b is coupled to the generation circuit 1016 at a gate 1048a-b of a transistor 1050a-b. The source 1052a of transistor 1050a is connected to a S signal bus line 1022a for S signal So and the source 1052b of transistor 1050b is connected to a S signal bus line 1022b for S signal Sn. The drains 1054a-b of each transistor 1050a-b are coupled together in a"wired-OR"configuration, represented by point 1056 and resistor 1057. Each transistor 1052a-b acts as a logical AND gate that selects its corresponding S signal when its gate 1048a-b is activated by the output 1046a-b of its corresponding latch circuit 1012a-b. Of course, there are alternative circuits to perform the functions of the invention that will be apparent to those skilled in the art. For instance, the transistors 1050a-b transistors may be replaced with integrated circuits that implement analog switches, AND, NAND or NOR gates. The wired OR portion 1056 and 1057 may similarly be replaced by one or more analog switches, OR, NAND, or NOR gates.

Once selected and combined by the generation circuit 1016, a combined S signal appears at the point 1056 and is coupled to the gate 1058 of a power transistor 1060 in the driver circuit 1024. The source 1062 of the power transistor 1060 is connect to a supply voltage 1064 and the drain 1066 of the power transistor 1060 is coupled to the load 1026 (e. g., a pixel).

As described above, the methods and systems of the present invention are particularly well suited to provide a pulse width modulated signal to a pixel element in a display. The following embodiments of the present invention (illustrated in FIGURES 7 and 8) describe a gray scale driver for a pixel element in a display. To simplify the following, discussion, it will be assumed that each pixel has a single monochromatic element having gray scale driven by the present invention. However, the following discussion can easily be applied to color systems. A color pixel includes three sub-pixels (RGB), each having their own gray scale and gray scale driver.

The following discussion also assumes that there are 256 (2) levels of gray scale for each pixel. The gray scale for the pixel is specified by a data word with 8 bits. As described above, any number of gray scale levels can be accommodated by the present invention by adjusting the number of data bits in the data word and/or available S signals. The following is also described in the context of using the invention in a digital device, with the pulse width modulated signal moving between a HIGH and a LOW voltage. For convenience in generating, timing and correlating the S signals to the bits of the data word, the S signals are binary weighted.

As illustrated in FIGURE 7A-B, the S Signals are square wave signals generated by a specialized counter system with different duty cycles and starting times related in the following manner: Signal So 1110 1X time period HIGH 1112 and starting immediately at the beginning of the cycle Signal Sl 1116 2X time periods HIGH 1118 and starting when 1112 Signal So goes LOW Signal S2 1122 4X time periods HIGH 1124 and starting when 1118 Signal Sl goes LOW Signal S3 1128 8X time periods HIGH 1130 and starting when 1124 Signal S2 goes LOW Signal S4 1134 16X time periods HIGH 1136 and starting when 1130 Signal S3 goes LOW Signal S5 1140 32X time periods HIGH 1142 and starting when 1136 Signal S4 goes LOW Signal S6 1146 64X time periods HIGH 1148 and starting when 1142 Signal S5 goes LOW Signal S7 1152 128X time periods HIGH 1154 and starting when 1148 Signal S6 goes LOW (For the next cycle, Signal So 1110 repeats again immediately after 1154 Signal S7 goes LOW)

In this embodiment, there would be eight gray scale bits representing a possible 256 possible levels of luminosity (zero luminosity plus 255 levels of gray). The total HIGH period for all S Signals ORed together would be 255 times the HIGH period for Signal So (this is known as the S Cycle time.) If a pixel is on for all of the entire S Cycle, it is then ON or HIGH for 100% of the time period since the cycle starts again after S7 goes LOW.

Signal So delivers 1/255 of the possible power to the pixel; Signal S1 delivers 2/255 of the possible power to the pixel; Signal S2 delivers 4/255 of the possible power to the pixel; Signal S3 delivers 8/255 of the possible power to the pixel; Signal S4 delivers 16/255 of the possible power to the pixel; Signal Ss delivers 32/255 of the possible power to the pixel; Signal S6 delivers 64/255 of the possible power to the pixel; Signal S7 delivers 128/255 of the possible power to the pixel.

As noted above, the number of S Signal lines is not restricted to eight lines but can be

as many or as few as are required to achieve the desired gray scale levels. For example, with sixteen S Signal lines, 65,536 level of gray scale are possible (zero luminosity plus 65,535 levels of gray). As more S Signal lines are added, each S Signal is 2 times longer than the previous S Signal and starts when the previous S Signal goes LOW. Therefore, as a new S Signal is added, the previous S Signal power levels are reduced by 1/2. Below are the signal relationships for a ten signal system: Signal So-1X time period HIGH, starting at the beginning of the cycle and delivers 1/1023 of the possible power to the pixel ; Signal S,-2X time periods HIGH, starting when Signal So goes LOW and delivers 2/1023 of the possible power to the pixel; Signal S2-4X time periods HIGH, starting when Signal Si goes LOW and delivers 4/1023 of the possible power to the pixel; Signal S3-8X time periods HIGH, starting when Signal S2 goes LOW and delivers 8/1023 of the possible power to the pixel; Signal S4-16X time periods HIGH, starting when Signal S3 goes LOW and delivers 16/1023 of the possible power to the pixel; Signal Ss-32X time periods HIGH, starting when Signal S4 goes LOW and delivers 32/1023 of the possible power to the pixel ; Signal S6-64X time periods HIGH, starting when Signal S5 goes LOW and delivers 64/1023 of the possible power to the pixel; Signal S7-128X time periods HIGH, starting when Signal S6 goes LOW and delivers 128/1023 of the possible power to the pixel; Signal S$-256X time periods HIGH, starting when Signal S7 goes LOW and delivers 256/1023 of the possible power to the pixel; Signal Sg-512X time periods HIGH, starting when Signal S8 goes LOW and delivers 512/1023 of the possible power to the pixel.

Since it is particularly suited to binary applications, the weight of the period"X"is selected in this embodiment as a power of 2 (i. e., X = 2n), although as described above, any weight value may be used.

In FIGURE 8A, an embodiment of the invention used to drive the gray scale of a plurality of pixel elements in a display is illustrated. As many gray scale drivers 1210a-b as are needed to drive the pixels in the display are coupled to an S signal bus 1212. For example, each sub-pixel (RGB) may have its own gray scale driver in an active matrix configuration or each column of sub-pixels (RGB) may have its own gray scale driver in a multiplexed configuration,. In this embodiment, each gray scale driver 1210a-b includes a

pre-load n-bit data latch 1214a-b that is coupled to a process n-bit latch 1216a-b. The process n-bit latch 1216a-b is coupled to a generation circuit 1220a-b. The generation circuit 1220a-b is coupled to a pixel driver 1222a-b, to which the generation circuit 1220a-b provides a combined S signal 512 such as is illustrated in FIGURE 4B. The S signal bus 1212, the process n-bit data latches 1216a-b, the pixel drivers 1222a-b and the generation circuits 1220a-b, are substantially similar to those described above with reference to FIGURES 5 and 6.

In operation, during a current S cycle the pixel driver 1222a-b is coupled to a composite S signal 1224a-b that is generated by the generation circuit 1220a-b in response to a plurality of data bit values that appear on corresponding outputs 1224a-f and 1225a-f of the process n-bit latch 1216a-b. The operation of the generation circuit 1220a-b is described in detail above with reference to FIGURES 5 and 6, but to review briefly the generation circuit selects corresponding constituent S signals from the S signal bus 1212 and outputs a composite S signal made up of the selected constituent S signals to the pixel drive 1222a-b.

The generation circuit shown in FIGURE 8A utilizes AND logic gates with output circuits connected in a WIRED OR configuration with resistor 1026a-b.

While the gray scale driver circuit outputs the composite S signal to the pixel driver 1222a-b, the pre-load n-bit latch 1214a-b is loaded with a data word 1230a-b that represents a desired duty cycle for the combined S signal to be sent to the pixel driver 1222a-b during a next S cycle.-At or near the start of the next S cycle, the data word 1230a-b is transferred from the pre-load n-bit latch 1214a-b to the process n-bit latch 1216a-b. The generation circuit 1220a-b generates the combined S signal for the pixel driver 1222a-b when the next S cycle becomes the current S cycle. In this way, the pre-load n-bit latch 1214a-b loads the data word 1230a-b for the duty cycle of the desired gray scale which will be displayed by the pixel during the next S cycle, while the process n-bit latch 1216a-b holds the data that the generation circuit uses to generate the combined S signal for the driver 1222a-b during the current S cycle.

FIGURE 8B illustrates another embodiment of a gray scale driver circuit formed in accordance with the present invention. The operation of the circuit in FIGURE 8B is essentially the same as just described for FIGURE 8A but it pre-loads the data word differently. In this embodiment, each gray scale driver 1210a-b loads the data word 1230a-b for the next S cycle directly into the n-bit process latch 1216a-b (bypassing the pre-load n-bit latch 1216a-b in the embodiment of FIGURE 8A) at a precise S cycle period during the current S cycle. The generation circuit 1220a-b generates the combined S signal for the pixel driver 1222a-b when the next S cycle becomes the current S cycle. The generation circuit

shown in FIGURE 8B utilizes AND logic gates with output circuits connected in a WIRED OR configuration with resistor 1026a-b.

In place of the pre-load n-bit latch 1216a-b in the embodiment of FIGURE 8A, in FIGURE 8B a single bit latch 1218a-b is coupled to an output 1219a-b of the data bit that corresponds to the S signal 1240 having the longest period (or any other S signal having a period long enough to load the data word 1230). The single bit latch 1218a-b is also coupled to an AND gate 1250a-b in the generation circuit 1220a-b also corresponding to the S signal 1240 having the longest period (or any other S signal having a period long enough to load the data word 1230).

Referring to FIGURES 7B, S signal S7 1154 has the longest period of the set of S signals, equaling approximately half the time allotted to the S cycle (128/255). At or before the time S signal S7 1154 goes HIGH, the bit value at output 1219a-b (FIGURE 8B) is loaded into the data latch 1218a-b. During the period that S signal S7 1154 is HIGH, the value stored by the data latch 1218a-b is used by the AND gate 1250a-b to decide whether to combine the S signal S7 1154 signal into the composite signal. Also during the S signal S7 1154 period, the other AND gates 1252a-b are disabled and the data word 1230a-b for the next S cycle is loaded into the process n-bit latch 1216a-b.

In this way, data latch 1218a-b takes the place of the pre-load n-bit latch 1214a-b shown in FIGURE 8A by allowing the new data for the next S cycle to be loaded directly into the process n-bit latch 1216a-b during the S7 period when the So-S6 output lines of the process n-bit latch 1216a-b are not used because the S signals So-Se are no longer HIGH. Any changes which occur on the So-S6 output lines of the process n-bit latch 1216a-b during the S7 period are ignored by the generation circuit 1220a-b and any change that occurs on the S7 output line of the process n-bit latch 1216a-b during the S7 period does not affect the generation circuit 1220a-b because the current S cycle data is stored in data latch 1218a-b.

An alternate method 200 of the present invention for generating a pulse width modulated signal with a programmable duty cycle is illustrated in FIGURE 9. The method 1300 begins in a block 1310 by generating a dot clock signal that includes a number of timed clock pulses. The dot clock signal is discussed in detail below with reference to FIGURES 10 and 11. The method 1300 employs a sequential data storage (block 1320) that stores data elements that can be read sequentially. Exemplary embodiments of the sequential data storage are described below with reference to FIGURES 12 and 13. In block 1330, a duty cycle for a desired pulse width modulated signal is specified by a data word that includes data elements that are associated with the timed clock pulses in the dot clock signal. The associations of the data word with the dot clock signal is discussed below in FIGURE 16.

The data elements from the data word are loaded into the sequential data storage in a block 1340. The data elements are read sequentially according to the timed clock pulses in the dot clock signal in a block 1350. The pulse width modulated signal is generated in a block 1360 by outputting a signal associated with the data element associated with the first clock pulse in the dot clock signal, then outputting a signal associated with the data element associated with the second clock pulse in the dot clock signal, and so on, until all the data elements have been output.

An exemplary dot clock signal 1410 is illustrated in FIGURE 10. The dot clock signal includes a number of S pulses that appear at defined intervals during the dot clock signal. In a preferred embodiment, the dot clock signal has a plurality of S pulses spaced in the dot clock signal according to a binary weighting formula. As discussed below, however, there are other ways to position the S pulses in the dot clock signal while remaining within the scope and spirit of the invention.

In FIGURE 10, the dot clock signal 1410a has a number (n) of S pulses 1416a-f that occur during a total period (T) 1412. The number (n) of S pulses is theoretically unlimited, but is generally decided by the resolution requirements for controlling the duty cycle of the output PWM signal for reasons discussed below. Each S pulse 1416a-g has its own unique place in time 1418a-g during the period T 1412. For example, in FIGURE 10, S pulse s° occurs at time period s°/T 1418a, S pulse sl occurs at time period sl/T 1418b, S pulse s2 occurs at time period s2/T 1418c, S pulse S3 occurs at time period s3/T 1418d, S pulse S4 occurs at time period s4/T 1418e, S pulse s occurs at time period s5/T 1418e, and so on, until the last two S pulses in the series are positioned with S pulse son-2 occurring at time period s' 2/T 1418f and S pulse s-'occurring at time period sn-1/T 1418g. For example, if the S pulses are binary weighted (s=2), signal s5 would occur at time 25/T.

The duration of the S pulses 1416a-f is sufficient to activate a shift input of a sequential data storage such as is described below in FIGURES 12 and 14. Either the leading or following edge of the S pulse may be used to activate the shift input and the S pulse positioned to correspond with the time period 1418a-f accordingly. The S pulses may also be implemented in software, for instance, with the S pulses 1416a-f representing software timer interrupts.

While binary weighting of the dot clock signal has certain advantages in digital applications (discussed below with reference to FIGURE 12), the S pulses 1416a-f do not have to be placed sequentially at time periods 1418a-f according to a weight value, but may be reordered in any pattern desired. Referring to FIGURE 11, one of many possible alternate dot clock signals 1510 is illustrated. The dot clock signal 1510 has five S pulses 1516a-e that

appear during a total period, or S-cycle (T) 1512, at time periods 1518a-e, respectively. As will become apparent in the discussion below, the intervals 1520a-e between the S pulses 1516a-e define the length of respective power supplying pulses in an output pulse width modulated (PWM) signal. The choice of the length of these intervals may affect the resolution and accuracy available in generating the output pulse width modulated signal but there may be many possible dot clock signals that would supply an output PWM signal within the tolerance of any given load. In the example dot clock signal 1510a, S pulse so 1516a occurs at time period (2.5/T) 1518a and has an interval 1520a from the start of the S cycle 1512 of 2.5/T. S pulse Si 1516b occurs at time period (18.75/T) 1518b and has an interval 1520b from S pulse so 1516a of 16.25/T. S pulse s2 1516c occurs at time period (19.75/T) 1518c and has an interval 1520c from S pulse Si 1516b of 1/T. S pulse s3 1516d occurs at time period (27.5/T) 1518d and has an interval 1520d from S pulse s2 1516c of 7.75/T. S pulse S4 1516e occurs at time period (31/1) 1518e and has an interval 1520e from S pulse S3 1516d of 3.5/T.

An embodiment of a programmable pulse width modulated signal generator 1610 is illustrated in FIGURE 12. The pulse width modulated generator 1610 includes a sequential data storage (shift register) 1612 and a driver 1614. The driver 1614 supplies a pulse width modulated power signal to a load 1615. The sequential data storage includes a plurality data latch circuits 1616a-c (such as D flip flops) connected together as a shift register. Generally, there will be a data latch circuit 1616a-c for each data element in a data word that specifies a desired duty cycle for the pulse width modulated signal to be generated. A shift input (often referred to as a clock input) 1620a-c of each data latch circuit 1616a-c is coupled to a dot clock signal (e. g., FIGURES 10-11).

One use for the pulse width modulated signal generator 1610 is to drive the gray scale of a pixel element in a display using a pulse width modulated signal. Because of timing constraints in this usage, it is desirable to pre-load a next data word for a next gray scale value as the current gray scale value is being generated using a current data word. A pre-load latch circuit 1630 is provided for this purpose. The pre-load latch circuit 1630 includes a plurality of latch circuits 1632a-c, with a latch circuit 1632a-c provided for each data element in the data word. The data latch circuits 1632a-c may be independent or configured as a shift register 1634 to receive the data word either from a parallel data bus 1636 or a serial data line 1638. The data word may be clocked into the shift register 1634 using a parallel load enable signal or bus clock 1640 that is coupled to each data latch circuit 1632a-c or loaded in parallel when a bus load enable signal 1642 that is also coupled to each data latch circuit 1632a-c is activated.

An output of each of the data latch circuits 1632a-c in the pre-load latch circuit 1630 is coupled to an input of a corresponding data latch circuit 1616a-c in the pulse width modulated generator 1610. In operation, a current data word is processed in the pulse width modulated signal generator 1610, as is described below with reference to FIGURE 13. While the current data word is being processed, a next data word is loaded into the pre-load latch circuit 1630 from the parallel data bus 1636 when the bus load enable 1642 is activated (or from the serial data line 1638 as the parallel load enable signal 1640 clocks the data into the shift register 1634. The next data word, now stored in the shift register 1634, is loaded into the pulse width modulated generator 1610 and is activated to be processed as the then current data word when a parallel load enable signal 1640 is activated. A new next data word is then loaded from the parallel data bus 1636 into the pre-load circuit 1630 and the process repeats.

The operation of the pulse width modulation generator 1610 is illustrated in FIGURE 13. To simplify the following discussion, the first four S pulses (1716a-d) from the dot clock signal 1410 (FIGURE 10) are shown separately as S pulses 1712a-d as they"enter"the shift input 1623 of the shift register 1612. A resulting (cumulative) PWM signal 1716a-d is shown following each S pulse 1712a-d at a driver output 1718a-d. The shift register 1612 in this example has four data latch circuits 1714a-d that are loaded with data elements"1101"from sample current data word. As discussed below, this data word may be coded in any convenient way, which in this example we will assume is a binary word. The data word "1101"equals a decimal 13 out of a possible 16 values (24) or a duty cycle of 13/16.

Each data element in the data word is associated with an S pulse 1712a-d. The data latch circuits 1714a-d are also associated with the S pulses 1712a-d in a shift order that corresponds with the arrival of the S pulses 1712a-d. The data elements (b3, b2, bl, bo) in the data word are loaded into their corresponding data latch circuits 1714a-d according to their associated S pulses 1712a-d. In FIGURE 13, data latch circuit 1714a is associated with S pulse so 1712a and loaded with bo = 1, data latch circuit 1714b is associated with S pulse si 1712b and loaded with b, = 0, data latch circuit 1714c is associated with S pulse s2 1712c and loaded with b2= 1, and data latch circuit 1714d is associated with S pulse S3 1712d and loaded with b3 = 1. The driver 1614 outputs the PWM signal based on a state of the data latch 1714a associated with the first S pulse so 1712a.

The generation of the PWM signal 1716a-d is illustrated in FIGURE 13 as a progression through four states 1720a-d of the shift register 1612. The shift register 1612 is configured in this example to preserve the data word by re-circulating the data elements in the shift register as they are shifted, as indicated by arrow 1721. In the first state 1720a of the shift register 1612, the data latch 1714a has a state"1"and the driver 1614 takes the output

1718a HIGH until the arrival of the so pulse 1712a. This results in a PWM pulse 1722a with a duration nearly equal to an interval 1724a from the beginning of the S cycle until the arrival of the S pulse so 1712a. The S pulse so 1712a defines the length of the PWM pulse 1722a by causing the shift register 1612 to shift the data elements, which in the next state 1720b, places the data elements"1110"into the data latch circuits 1714d, 1714c, 1714b and 1714a, respectively.

In the second state 1720b of the shift register 1612, the data latch 1714a has a state "0"and the driver 1614 takes the output 1718b LOW until the arrival of the sl pulse 1712b.

This results in a LOW PWM pulse 1722b (shown at zero) with a duration nearly equal to an interval 1724b from the arrival of the S pulse so 1712a until the arrival of the S pulse si 1712b. The S pulse sI 1712b defines the length of the PWM pulse 1722b by causing the shift register 1612 to shift the data elements, which in the next state 1720c, places the data elements"0111"into the data latch circuits 1714d, 1714c, 1714b and 1714, respectively.

In the third state 620c of the shift register 1612, the data latch 1714a has a state"1" and the driver 1614 takes the output 1718c HIGH until the arrival of the s2 pulse 1712c. This results in a HIGH PWM pulse 1722c-with a duration nearly equal to an interval 1724c from the arrival of the S pulse sl 1712b until the arrival of the S pulse s2 1712c. The S pulse s2 1712c defines the length of the PWM pulse 1722c by causing the shift register 1612 to shift the data elements, which in the next state 1720d, places the data elements"1011"into the data latch circuits 1714d, 1714c, 1714b and 1714a, respectively.

In the fourth state 1720d of the shift register 1612, the data latch 1714a has a state"1" and the driver 1614 takes the output 1718d HIGH until the arrival of the S3 pulse 1712d. This results in a HIGH PWM pulse 1722d with a duration nearly equal to an interval 1724d from the arrival of the S pulse s2 1712c until the arrival of the S pulse S3 1712d. The S pulse S3 1712d defines the length of the PWM pulse 1722d by causing the shift register 1612 to shift the data elements, which in the next state 1720d, places the data elements"1101"into the data latch circuits 1714d, 1714c, 1714b and 1714a, respectively. Following the fourth state 1720d, the current S cycle is concluded and the next S cycle begins. A new data word can be loaded into the shift register 1612 for the next S cycle, or the data word that is currently in the shift register 1612 can be reused.

Another embodiment of a programmable pulse width modulated generator 1810 is illustrated in FIGURE 14. The pulse width modulated generator 1810 includes a sequential data storage 1812 and a driver 1814. The driver supplies a pulse width modulated power signal to a load 1815, which is the preferred embodiment is a pixel in a display. The sequential data storage includes a plurality data latch circuits 1816a-c (such as D flip flops)

connected together as a shift register 1818. Generally, there will be a data latch circuit 1816a- c for each data element in a data word that specifies a desired duty cycle for the pulse width modulated signal to be generated.

The data word is preferably loaded into the data latch circuits 1816a-c through a parallel data bus 1820 when activated by a parallel load enable 1822. The data word may alternatively be loaded from a serial data connection 1824 into the shift register 1818 by activating a common shift input. An additional data latch 1816d is connected in series with data latches 1816a-c. As will be discussed in detail below with reference to FIGURE 15, the additional data latch 1816d provides storage for the processing of one or more data elements in a data word while a next data word is being loaded into the shift register 1818. A dot clock 1826 (FIGURES 10-11) is coupled to the shift input. To facilitate the reuse the data word over more than one S cycle, a feedback loop 1828 couples an output to an input of the shift register 1818 (the output of the data latch circuit 1816c to the serial input of the first 1816a data latch circuit). Data latch circuit 1816d may also be included in the re-circulation of the data word, as is discussed below in FIGURE 15.

The operation of the pulse width modulation generator 1810 is illustrated in FIGURE 15. As in the discussion of FIGURE 8, the first four S pulses (1416a-d) from the dot clock signal 1410 (FIGURE 10) are shown separately as S pulses 1912a-d as they"enter"the shift input of the shift register 1818. A resulting (cumulative) PWM signal 1916a-d is shown following each S pulse 1912a-d at a driver output 1918a-e. The shift register 1818 in this example has four data latch circuits 1914a-d that are loaded with data elements"1101"from sample current data word. As discussed below, this data word may be coded in any convenient way, which in this example we will assume is a binary word. The data word "1101"equals a decimal 13 out of a possible 16 values (24) or a duty cycle of 13/16.

Each data element in the data word is associated with an S pulse 1912a-d. The data latch circuits 1914a-d are also associated with the S pulses 1912a-d in a shift order that corresponds with the arrival of the S pulses 1912a-d. The data elements (b3, b2, bl, bO) in the data word are loaded into their corresponding data latch circuits 1914a-d according to their associated S pulses 1912a-d. In FIGURE 15, data latch circuit 1914a is associated with S pulse sO 1912a and loaded with bO = 1, data latch circuit 1914b is associated with S pulse s1 1912b and loaded with bl = 0, data latch circuit 1914c is associated with S pulse s2 1912c and loaded with b2 = 1, and data latch circuit 1914d is associated with S pulse s4 1912d and loaded with b3 = 1. The driver 1614 outputs the PWM signal based on a state of the data latch 1914a associated with the first S pulse sO 1912a.

The generation of the PWM signal 1916a-d is illustrated in FIGURE 15 as a progression through four states of the shift register 1818. The shift register 1818 is configured in this example to preserve the data word by re-circulating the data elements in the shift register as they are shifted, as indicated by arrow 1921. In the first state of the shift register 1818, the data latch 1914a has a state"1"and the driver 1614 takes the output 1918a HIGH until the arrival of the sO pulse 1912a. This results in a PWM pulse 1922a with a duration nearly equal to an interval 1924a from the beginning of the S cycle until the arrival of the S pulse sO 1912a. The S pulse sO 1912a defines the length of the PWM pulse 1922a by causing the shift register 1818 to shift the data elements, which in the next state 1920b, places the data elements"1110"into the data latch circuits 1914d, 1914c, 1914b and 1914a, respectively.

In the second state of the shift register 1818, the data latch 1914a has a state"0"and the driver 1614 takes the output 1918b LOW until the arrival of the s1 pulse 1912b. This results in a LOW PWM pulse 1922b (shown at zero) with a duration nearly equal to an interval 1924b from the arrival of the S pulse sO 1912a until the arrival of the S pulse s1 1912b. The S pulse s1 1912b defines the length of the PWM pulse 1922b by causing the shift register 1818 to shift the data elements, which in the next state, places the data elements "0111"into the data latch circuits 1914d, 1914c, 1914b and 1914a, respectively.

In the third state of the shift register 1818, the data latch 1914a has a state"1"and the driver 1614 takes the output 1918c HIGH until the arrival of the s2 pulse 1912c. This results in a HIGH PWM pulse 1922c with a duration nearly equal to an interval 1924c from the arrival of the S pulse s1 1912b until the arrival of the S pulse s21912c. The S pulse s2 1912c defines the length of the PWM pulse 1922c by causing the shift register 1818 to shift the data elements, which in the next state, places the data elements"1011"into the data latch circuits 1914d, 1914c, 1914b and 1914a, respectively.

In the fourth state of the shift register 1818, the data latch 1914a has a state"1"and the driver 1614 takes the output 1918d HIGH until the arrival of the s3 pulse 1912d. This results in a HIGH PWM pulse 1922d with a duration nearly equal to an interval 1924d from the arrival of the S pulse s2 1912c until the arrival of the S pulse s3 1912d. The S pulse s4 1912d defines the length of the PWM pulse 1922d by causing the shift register 1818 to shift the data elements, which in the next state 1920d, places the data elements"1101"into the data latch circuits 1914d, 1914c, 1914b and 1914a, respectively. Following the fourth state, the current S cycle is concluded and the next S cycle begins. A new data word can be loaded into the shift register 1818 for the next S cycle, or the data word that is currently in the shift register 1818 can be reused.

The preceding examples have assumed a binary data word that is loaded into a standard shift register that are shifted according to a binary weighted dot clock signal to an shift register output with a least significant bit appearing in the output first and a most significant bit appearing in the output last. As was discussed above with reference to FIGURES 10A and B, the dot clock signal does not have to be binary weighted. Similarly, there are many modification that may be made to the above examples that remain within the spirit and scope of the invention. For instance, a data word 2012 may be mapped to a set of S pulses 2014a-d in an order. In FIGURE 16, S pulse s2 2014a is mapped to b3 2016a, S pulse so 2014b is mapped to b2 2016b, S pulse sl 2014c is mapped to bi 2016c, and S pulse S3 2014d is mapped to bo 2016d.

The data elements 2016a-d in the data word 2012 are loaded into a shift register in the sequential order that the S pulses are input to the shift register 2018. In FIGURE 16, the shift register 2018 is configured to shift from right to left (arrow 2020). A driver 2022 is coupled to a data storage circuit 2026 that is associated with the first S pulse to arrive at the shift register input. In the example illustrated in FIGURE 16, the binary equivalent of the data word is"0011", which when considering the mapping just described indicates a duty cycle of 3/16. Using a dot clock signal 2030, that is broken into pulses 2014a-d in the illustration, a PWM signal 2032a-d is generated in much the same manner that is described above in FIGURES 13 and 15.

In the example, the data storage circuit 2026 contains the initially loaded value"0", which causes the driver to output a LOW PWM pulse 2040a until the so pulse 2014a is input to the shift register 2018. The so pulse shifts the data elements to the left, entering a"1"in the data storage circuit 2026, which causes the driver 2022 to output a HIGH PWM pulse 2040b until the Si pulse 2014b is input to the shift register 2018. The s1 pulse shifts the data elements to the left, entering a"0"in the data storage circuit 2026, which causes the driver 2022 to output a LOW PWM pulse 2040c until the sa pulse 2014c is input to the shift register 2018. The s2 pulse shifts the data elements to the left, entering a"1"in the data storage circuit 2026, which causes the driver 2022 to output a HIGH PWM pulse 2040d until the S3 pulse 2014b is input to the shift register 2018. The s3 pulse shifts the data back to the original order of the data word, which may be used again or a new data word loaded, as discussed above. As the PWM signal 2040d illustrates, the timing of the S pulses 2014a-d together with the order and shifting of the data word in the shift register 2018 yield a PWM signal with a duty cycle of 3/16, as specified in the data word 2012.

While the preferred embodiment of the invention has been illustrated and described, many changes can be made without departing from the spirit and scope of the invention. the invention is not limited by the disclosure of the preferred embodiment. Instead, the invention should be determined entirely by reference to the claims that follow.