METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER

Title:

METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER

Document Type and Number:

WIPO Patent Application WO/2006/033292

Kind Code:

A1

Abstract:

A method for manufacturing a semiconductor wafer, characterized in that it comprises a process of epitaxially growing an Si_1-XGe_X layer (0 ≤ X ≤ 1) on an SOI wafer, and forming an Si_1-YGe_Y layer (0 ≤ Y < X) on the resultant epitaxially grown Si_1-XGe_X layer, followed by subjecting to a treatment of oxidation under heating, to thereby concentrate the Ge in the above epitaxially grown Si_1-XGe_X layer and form a concentrated SiGe layer, wherein the above treatment of oxidation under heating comprises starting it from a temperature of 950&ring C or less and allowing the oxidation to proceed so as for the above formed Si_1-YGe_Y layer to remain till the rise of the temperature to 950&ring C. The above method for manufacturing a semiconductor wafer allows the satisfactory lattice relaxation of the SiGe layer of an SGOI wafer to be carried out with a heat treatment for a short time, which results in the lowering of the production cost of the wafer.

Inventors:

YOKOKAWA ISAO (JP)
NOTO NOBUHIKO (JP)
MITANI KIYOSHI (JP)

Application Number:

PCT/JP2005/017120

Publication Date:

March 30, 2006

Filing Date:

September 16, 2005

Export Citation:

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Assignee:

SHINETSU HANDOTAI KK (JP)
YOKOKAWA ISAO (JP)
NOTO NOBUHIKO (JP)
MITANI KIYOSHI (JP)

International Classes:

H01L21/20; H01L21/02; H01L27/12

Foreign References:

JP2000243946A	2000-09-08
JP2004040122A	2004-02-05
JP2004363197A	2004-12-24
JP2004363198A	2004-12-24
JP2004363199A	2004-12-24
JP2005050984A	2005-02-24

Other References: