METHOD FOR MANUFACTURING STACKED ELECTRONIC COMPONENT

WIPO Patent Application WO/2007/105395

A1

This invention provides a method for manufacturing a stacked electronic component which has an excellent effective volume ratio and is highly reliable. In the manufacturing method, a laminate in its predetermined face at its sites where each end of a plurality of internal electrodes is exposed, is directly subjected to electroless plating to form a thin and highly dense external electrode. In carrying out the step of electroless plating for external electrode (8, 9) formation, a plating solution containing a reducing agent and a metal ion having a deposition potential which is electrochemically more noble than the redox potential of the reducing agent is provided. A laminate (5) for stacked electronic components, together with electroconductive media having catalytic activity against an oxidation reaction of the reducing agent, is placed in a vessel, followed by stirring of the laminate (5) and the electroconductive media in the plating solution by rotation, swinging, slanting, or vibration. In this case, electroless plating proceeds so that plating deposits (12a, 12b) deposited on the end of a plurality of internal electrodes (3a, 3b) are connected to each other.

KUNISHI TATSUO (JP)
OGAWA MAKOTO (JP)
MOTOKI AKIHIRO (JP)

PCT/JP2007/052455

September 20, 2007

February 13, 2007

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MURATA MANUFACTURING CO (JP)
KUNISHI TATSUO (JP)
OGAWA MAKOTO (JP)
MOTOKI AKIHIRO (JP)

H01G4/30; H01G4/12

JP2003183843A	2003-07-03
JPH10208978A	1998-08-07
JPS63169014A	1988-07-13

KOSHIBA, Masaaki (Nisshin Buiding 14-22, Shitennoji 1-chome, Tennoji-ku, Osaka-sh, Osaka 51, JP)

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