Title:
METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, AND THIN FILM TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2010/104005
Kind Code:
A1
Abstract:
Disclosed are: a method for manufacturing a thin film transistor with excellent productivity, wherein a barrier layer (a bank) can be appropriately formed; and a thin film transistor. Specifically disclosed is a method for manufacturing a thin film transistor which is provided with a semiconductor film in a channel part between the source electrode and the drain electrode. The method for manufacturing a thin film transistor comprises: a step wherein two base electrode layers, on the surfaces of which the source electrode and the drain electrode are to be formed respectively, are formed on the surface of a base layer; a step wherein a barrier layer is formed on the surface of the base layer containing the two base electrode layers so as to surround the regions of the two base electrode layers, on said regions the source electrode and the drain electrode being to be formed respectively; a step wherein the source electrode and the drain electrode are formed by a plating method respectively on the surfaces of the two base electrode layers, which are surrounded by the barrier layer; and a step wherein a semiconductor solution, in which a semiconductor material is dissolved or dispersed, is applied to the region surrounded by the barrier layer after the formation of the source electrode and the drain electrode, so that a semiconductor film is formed in the region.
Inventors:
YAMADA JUN (JP)
Application Number:
PCT/JP2010/053644
Publication Date:
September 16, 2010
Filing Date:
March 05, 2010
Export Citation:
Assignee:
KONICA MINOLTA HOLDINGS INC (JP)
YAMADA JUN (JP)
YAMADA JUN (JP)
International Classes:
H01L21/336; G02F1/1343; G02F1/1368; H01L21/28; H01L29/417; H01L29/786; H01L51/05; H01L51/40
Foreign References:
| JP2009010332A | 2009-01-15 | |||
| JP2007036259A | 2007-02-08 | |||
| JP2006114862A | 2006-04-27 |
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