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Title:
METHOD FOR OPTIMIZING PCB INNER LAYER PATTERN, PCB, BOARD SPLICED STRUCTURE AND LAMINATED STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2019/056650
Kind Code:
A1
Abstract:
A method for optimizing a PCB inner layer pattern, a PCB, a board spliced structure, and a laminated structure. A PCB inner layer pattern comprises a copper region (600) and a copper-free region (100); the copper-free region (100) comprises a via hole region (10) having at least one via hole (11); when a residual copper rate of the copper region (600) is less than a specific value, copper dots (12) are laid out at the positions of the via holes (11), and the diameter of the copper dot (12) is less than that of the via hole (11). Such small-size copper dots laid out can improve distribution uniformity of the pattern and reduce the volume of glue required for glue filling in the copper-free region, so that risks of wrinkling, cavities and the like of a copper foil subjected to lamination processing can be reduced. Moreover, the size of the copper dot is less than that of the via hole, so that the copper dots can be drilled off during drilling. In addition, layout of the copper dots can further promote PCB drilling quality to a certain degree and particularly has a great improvement effect on drilling haloing, so that CAF performance of the PCB is improved.

Inventors:
CHENG LIUJUN (CN)
CHEN BEI (CN)
LI YANGUO (CN)
LI HUA (CN)
Application Number:
PCT/CN2017/120099
Publication Date:
March 28, 2019
Filing Date:
December 29, 2017
Export Citation:
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Assignee:
GUANGZHOU FASTPRINT CIRCUIT TECH CO LTD (CN)
SHENZHEN FASTPRINT CIRCUIT TECH CO LTD (CN)
YIXING SILICON VALLEY ELECTRONICS TECH CO LTD (CN)
International Classes:
H05K1/11; H05K1/14
Foreign References:
CN203645911U2014-06-11
CN103533760A2014-01-22
CN104582285A2015-04-29
CN101547555A2009-09-30
JPH08279678A1996-10-22
Attorney, Agent or Firm:
ADVANCE CHINA IP LAW OFFICE (CN)
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