Title:
METHOD FOR OPTIMIZING PROTECTION CIRCUITS OF ELECTRONIC DEVICE CHIPS IN WAFER
Document Type and Number:
WIPO Patent Application WO/2024/000184
Kind Code:
A1
Abstract:
A method for wafer-level optimization of protection circuits of nitride-based electronic device chips in a wafer is provided. The method comprises: fabricating an adjustment circuit in the wafer for each of the protection circuits, the adjustment circuit including one or more fuse elements connected respectively in parallel with one or more protection devices in the protection circuit; and adjusting each of the protection circuits by trimming one or more to-be-trimmed fuse elements corresponding to the protection circuit. The trimming of the to-be-trimmed fuse elements is performed by applying a photoresist layer on the wafer; patterning the photoresist layer with a one-to-one photomask to expose the to-be-trimmed fuse elements; and etching away the to-be-trimmed fuse elements. By using the one-to-one photomask, complete wafer coverage can be achieved without stepping the wafer repeatedly from position to position for exposure. Therefore, complexity of photomask alignment and exposure errors can be greatly reduced.
More Like This:
| JP4140232 | Semiconductor device |
Inventors:
YOU JHENG-SHENG (CN)
DU WEIXING (CN)
DU WEIXING (CN)
Application Number:
PCT/CN2022/101998
Publication Date:
January 04, 2024
Filing Date:
June 28, 2022
Export Citation:
Assignee:
INNOSCIENCE SUZHOU SEMICONDUCTOR CO LTD (CN)
International Classes:
H01L27/02
Domestic Patent References:
| WO2021217400A1 | 2021-11-04 |
Foreign References:
| US20090197156A1 | 2009-08-06 | |||
| US20150372096A1 | 2015-12-24 | |||
| US20210210955A1 | 2021-07-08 | |||
| US7285458B2 | 2007-10-23 | |||
| US10381828B1 | 2019-08-13 |
Attorney, Agent or Firm:
BEIJING BESTIPR INTELLECTUAL PROPERTY LAW CORPORATION (CN)
Download PDF: