Title:
METHOD FOR PRODUCING SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING LAMINATE
Document Type and Number:
WIPO Patent Application WO/2017/057355
Kind Code:
A1
Abstract:
Provided are: a method for producing a semiconductor element, which effectively suppresses die shift and exhibits excellent separation properties between a temporary adhesive layer and a molding layer; and a method for producing a laminate.
A method for producing a semiconductor element, wherein a member that has a temporary adhesive layer on a carrier substrate and a die that has a circuit on at least one surface thereof are pressure-bonded with each other at a temperature T1 in such a manner that the temporary adhesive layer is in contact with the die, and after forming a molding layer at a temperature T2 on a surface of the die, said surface being on the reverse side of the surface in contact with the temporary adhesive layer, the carrier substrate is separated at a temperature of 40°C or less. In this connection, the temperature T1 is a temperature at which the melt viscosity of the temporary adhesive layer as measured at a measurement frequency of 10 Hz is from 4,000 Pa·s to 10,000 Pa·s (inclusive); and the temperature T2 is a temperature at which the melt viscosity of the temporary adhesive layer as measured at a measurement frequency of 10 Hz is 4,000 Pa·s or more.
Inventors:
KAMOCHI YOSHITAKA (JP)
NAKAMURA ATSUSHI (BE)
NAKAMURA ATSUSHI (BE)
Application Number:
PCT/JP2016/078438
Publication Date:
April 06, 2017
Filing Date:
September 27, 2016
Export Citation:
Assignee:
FUJIFILM CORP (JP)
International Classes:
H01L21/56
Foreign References:
| JP2013074184A | 2013-04-22 | |||
| JP2012129326A | 2012-07-05 | |||
| JP2012069919A | 2012-04-05 | |||
| JP2015050268A | 2015-03-16 |
Attorney, Agent or Firm:
SIKS & CO. (JP)
Download PDF: