Title:
METHOD FOR PRODUCING WIRING BOARD, METHOD FOR EVALUATING RESIST LAYER OR WIRING BOARD, AND WIRING BOARD
Document Type and Number:
WIPO Patent Application WO/2024/034068
Kind Code:
A1
Abstract:
The present invention provides a method for producing a wiring board, the method comprising: a step for forming a resist layer on a seed layer that contains a metal and is arranged on a main surface of a substrate; a step for exposing the resist layer to light and developing the resist layer so as to provide the resist layer with a pattern that comprises an opening from which the seed layer is exposed; and a step for forming a copper plating layer on the seed layer, which is exposed in the opening, by means of electrolytic plating. The copper plating layer is formed so that the BP occupancy, which is the occupancy of a black part in the width direction of the copper plating layer, the black part being observed in a cross-section of a metal part that contains the seed layer and the copper plating layer, is 45% or less. The resist layer is selected. The BP occupancy is a value that is determined by a method that comprises a calculation of the BP occupancy by the formula.
Inventors:
TOGASAKI KEI (JP)
IWASHITA KENICHI (JP)
ONO KEISHI (JP)
NARITA MAO (JP)
MITSUKURA KAZUYUKI (JP)
TOBA MASAYA (JP)
IWASHITA KENICHI (JP)
ONO KEISHI (JP)
NARITA MAO (JP)
MITSUKURA KAZUYUKI (JP)
TOBA MASAYA (JP)
Application Number:
PCT/JP2022/030593
Publication Date:
February 15, 2024
Filing Date:
August 10, 2022
Export Citation:
Assignee:
RESONAC CORP (JP)
International Classes:
H05K3/00; H05K3/18
Domestic Patent References:
| WO2022054873A1 | 2022-03-17 |
Attorney, Agent or Firm:
HASEGAWA Yoshiki et al. (JP)
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