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Patent Searching and Data


Title:
METHOD FOR PRODUCING WIRING BOARD
Document Type and Number:
WIPO Patent Application WO/2022/102182
Kind Code:
A1
Abstract:
The present invention provides a method for producing a wiring board, said method being capable of suppressing damage on a device layer at the time of carrier separation, while being capable of performing a photolithography process on the device layer with high accuracy after the carrier separation. This method for producing a wiring board comprises: a step for preparing a multilayer sheet that sequentially comprises, on a carrier, a release layer, a metal layer and a device layer; a step for making a cut line from the carrier-side surface of the multilayer sheet in such a manner that the cut line passes inside the outline of the device layer and both ends of the cut line reach the ends of the multilayer sheet when viewed in plan, while the cut line penetrates through the carrier, the release layer and the metal layer when viewed in cross section; and a step for removing peripheral portions of the carrier, the release layer and the metal layer, said peripheral portions being positioned outside the cut line, thereby having a part of the metal layer-side surface of the device layer exposed so as to form a pressurizable exposed part for accelerating separation of the carrier.

Inventors:
KITABATAKE YUKIKO (JP)
YANAI TAKENORI (JP)
MATSUURA YOSHINORI (JP)
Application Number:
PCT/JP2021/029415
Publication Date:
May 19, 2022
Filing Date:
August 06, 2021
Export Citation:
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Assignee:
MITSUI MINING & SMELTING CO LTD (JP)
International Classes:
H01L23/12; H05K3/00
Domestic Patent References:
WO2018066114A12018-04-12
WO2017150283A12017-09-08
WO2017150284A12017-09-08
Foreign References:
JP2011228613A2011-11-10
JP2011238895A2011-11-24
JP2014072440A2014-04-21
JP2005101137A2005-04-14
JP2015035551A2015-02-19
JP2020119952A2020-08-06
JP2020027888A2020-02-20
Other References:
See also references of EP 4246565A4
Attorney, Agent or Firm:
TAKAMURA Masaharu et al. (JP)
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