Title:
METHOD FOR REDUCING PARASITIC COUPLINGS IN CIRCUITS
Document Type and Number:
WIPO Patent Application WO2005041273
Kind Code:
A3
Abstract:
The invention relates to a method for reducing parasitic couplings in circuits in which dummy structures are embedded in previous production method steps. The invention aims at providing a method that makes it possible to improve decoupling values and reduce the degree of complexity of said method. This is achieved in that the dummy structures (3) are removed at least partly by means of etching steps and cavities (4) are produced.
Inventors:
HELNEDER JOHANN (DE)
SCHWERD MARKUS (DE)
GOEBEL THOMAS (DE)
MITCHELL ANDREA (DE)
KOERNER HEINRICH (DE)
DREXL STEFAN (DE)
SECK MARTIN (DE)
SCHWERD MARKUS (DE)
GOEBEL THOMAS (DE)
MITCHELL ANDREA (DE)
KOERNER HEINRICH (DE)
DREXL STEFAN (DE)
SECK MARTIN (DE)
Application Number:
PCT/DE2004/002266
Publication Date:
September 09, 2005
Filing Date:
October 12, 2004
Export Citation:
Assignee:
INFINEON TECHNOLOGIES AG (DE)
HELNEDER JOHANN (DE)
SCHWERD MARKUS (DE)
GOEBEL THOMAS (DE)
MITCHELL ANDREA (DE)
KOERNER HEINRICH (DE)
DREXL STEFAN (DE)
SECK MARTIN (DE)
HELNEDER JOHANN (DE)
SCHWERD MARKUS (DE)
GOEBEL THOMAS (DE)
MITCHELL ANDREA (DE)
KOERNER HEINRICH (DE)
DREXL STEFAN (DE)
SECK MARTIN (DE)
International Classes:
H01L21/768; H01L23/522; H01L23/532; (IPC1-7): H01L21/768; H01L23/522
Foreign References:
| US20030173674A1 | 2003-09-18 | |||
| US20030146513A1 | 2003-08-07 | |||
| US20020000663A1 | 2002-01-03 |
Other References:
PATENT ABSTRACTS OF JAPAN vol. 017, no. 579 (E - 1451) 21 October 1993 (1993-10-21)
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