RELATED APPLICATIONS

[0001] This is the first application filed for the present invention.

FIELD OF THE INVENTION

[0002] The present invention generally pertains to the field of optical logic elements and in particular to methods and systems for measuring photon counts in electro-optical circuits and producing corresponding electronic and optical signals.

BACKGROUND

[0003] Over the past decade, neural network models have been playing a significant role in Machine Learning, thanks to major algorithmic innovations and new hardware, specifically graphical processing units (GPUs). But today, even GPUs are pushed to their limits, thus demanding the development of new hardware to accelerate machine learning computations. Various research groups and technology-based companies, including Google LLC, IBM, Intel Corporation, Microsoft Corporation and Amazon.com Inc., have heavily invested in massively parallel application-specific integrated circuits (ASICs), to accelerate the computations required in neural network models.

[0004] A very promising alternative to GPUs is optical computing using silicon photonics, which allows an implementation of photonic circuits, integrated with complementary metal oxide semiconductor (CMOS) chips for electronic control, and is expected to lead to ultrafast information processing.

[0005] An efficient and competitive optical computing hardware structure requires the implementation of various attributes of digital optical logic, including low power consumption, high algorithmic or computational efficiency, no capacitive loading effects, no crosstalk between signals, high speed operation, high noise margins, and high fan-in/fan-out. The photodetectors used in these structures play a significant role in meeting the requirements of an optical computing system.

[0006] Some of these structures are known as neuromorphic photonic processors and they join a class of photonic hardware accelerators that are designed to assist in the acquisition, feature extraction, and storage of wideband waveforms. These accelerators manipulate the spectro-temporal profile of a wideband signal, a task difficult to accomplish using analog electronics over broad bandwidth and with low loss.

[0007] There are many challenges involved in the implementation of photonic computing architectures including: mitigating the noise inherent to analog building blocks, limited computational efficiencies, nonlinearities associated with the photonic components, and scalability. In order for these architectures to be widely adopted for optical computing, the bottlenecks need to be solved. This can lead to the efficient integration of well-defined photonic neurons and neural interconnects upon a common photonic-electronic platform.

[0008] One limitation in particular, is that the current state-of-the-art photodetectors (PD) that can be used as sensitive optical receivers in photonic computing systems, have limited responsivity and suffer from high excess noise.

[0009] Therefore, there is a need for a detection method or system that can obviate or mitigate one or more limitations of the prior art in photonic processing by exhibiting greater speed and responsivity, greater efficiency, less noise, less nonlinearities, and improved scalability.

[0010] This background information is provided to reveal information believed by the applicant to be of possible relevance to the present invention. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present invention

SUMMARY [0011] Issues involved in the physical implementation of neuromorphic computing can be resolved with the introduction of single-photon avalanche diodes (SPAD) as photodetectors in the systems, especially in an array configuration. By using an array of SPADs, subdividing the array into subarrays, and activating each subarray successively such that the array as a whole always has at least one activated subarray at any given time, the array can act as an individual photo detector with many benefits over a common photodetector. The use of two SPAD arrays at the output of an add-drop configuration of modulated optical elements can be used to implement the accumulation portion of a multiply-and-accumulation optical circuit, by taking into account the negative terms and also the dark count rate inherent to SPADs. Benefits for optical computing include lower energy consumption, higher responsivity, lower noise, digital domain, and others.

[0012] An aspect of the disclosure provides a method for detecting an optical input signal by receiving an optical signal by an optical detector array divided into a plurality of subarrays such that each subarray includes a plurality of optical detectors; activating the subarrays in sequence by applying a voltage signal to each optical detector of a subarray substantially simultaneously, while substantially simultaneously deactivating and leaving deactivated the optical detectors of other subarrays until a further iteration of the sequence; and recharging the deactivated optical detectors of the array. In an embodiment, each subarray can be connected to a dedicated counter and an output of each activated subarray can represent a photon count. In an embodiment, the photon count of each dedicated counter can be registered in a non-transient memory. In an embodiment, a time-gating sequence of activating and deactivating the subarrays of an array can be reiterated indefinitely and until stopped. In an embodiment, activating a subarray can comprise applying bias voltages to its optical detectors, and deactivating a subarray can comprise removing bias voltages from its optical detectors. In an embodiment, activating and deactivating a subarray can be performed by a voltage-controlled oscillator, a variable delay block, a pulse-width modulator, and a buffer. In an embodiment, each optical detector of an array can be a single-photon avalanche diode (SPAD). In an embodiment, each optical detector of the array can be a superconducting nanowire single photon detector (SNSPD). [0013] An aspect of the disclosure provides a system for performing optical computations that can include at least one optical waveguide for propagating an optical input signal; at least one row of at least one optical element, each optical element modulated by an electrical input signal and each optical element for producing a correspondingly modulated optical output signal from the optical input signal; and at least one single-photon avalanche diode (SPAD) for receiving the optical output signal modulated by the at least one optical element. In an embodiment, a system can include a plurality of SPADs, configured as a SPAD array for receiving an optical output signal; the SPAD array can be divided into a plurality of SPAD subarrays such that each SPAD subarray includes at least one SPAD, and each SPAD subarray can be connected to timing-gating circuitry for activating and deactivating the SPAD subarrays, one at a time in sequence; and each SPAD subarray can be connected to a dedicated counter. In an embodiment, a system can include at least one SPAD that can be time-gated according to parameters including a SPAD activation duration, a SPAD deactivation duration, and a rate at which activation and deactivation can occur; a SPAD activation allowing its operation, and a deactivation allowing its recharge. In an embodiment, each optical element of a system for performing optical computations can be a modulated microring resonator (MRR) having a drop port for transmitting an optical signal to a first SPAD array, and a through port for transmitting an optical signal to a second SPAD array; and the outputs from the first and second SPAD arrays can be received by a same subtractor. In an embodiment, an optical element of a system for performing optical computations has a drop port and a through port, and the outputs from each row of optical elements can be received, through a first and second arrays of SPADs, by a respective subtractor. In an embodiment, a laser source can be connected to each subtractor collecting the output of a row of optical elements through SPAD arrays, such that each laser source can be modulated by the output of a subtractor. In an embodiment, at least one laser source is modulated by the output of a subtractor, and a wavelength division multiplexer (WDM) can receive optical signals from each modulated laser source and multiplex the optical signals into a single output.

BRIEF DESCRIPTION OF THE DRAWINGS [0014] Fig. la illustrates an electro-optical architecture where a balanced photodetector is directly connected to an optical modulator.

[0015] Fig. lb illustrates how a neuron can be emulated with a microring resonator used in an add-drop configuration.

[0016] Fig. 2a is a diagram representing the broadcast-and-weight protocol for neuromorphic photonics, according to an embodiment. .

[0017] Fig. 2b illustrates an architecture for a matrix loading and photonic computing block, according to an embodiment.

[0018] Fig. 3 is a block diagram of a counting module for a SPAD photodetector, according to an embodiment.

[0019] Fig. 4a illustrates a train of periodically time-gated pulses, generated to activate a time gated SPAD (TG-SPAD), according to an embodiment.

[0020] Fig. 4b illustrates a hardware configuration for generating a time-gate signal, according to an embodiment.

[0021] Fig. 5 illustrates a TG-SPAD array architecture, according to an embodiment.

[0022] Fig. 6 illustrates an architecture for a subarray (SA) of 16 SPAD photodetectors and their frontend circuitry, according to an embodiment.

[0023] Fig. 7 illustrates frontend circuitry for a TG-SPAD that is part of a SPAD subarray, according to an embodiment, and is divided into Fig. 7a, Fig. 7b, Fig. 7c, and Fig. 7d, according to an embodiment.

[0024] Fig. 7a shows how a voltage signal of operation, time-gating, quenching and a reset operation can be applied to a photodetector, according to an embodiment. [0025] Fig. 7b shows how transistors can be used to detect the voltage on the photodetector, according to an embodiment.

[0026] Fig. 7c shows circuitry to count the number of detection events, according to an embodiment.

[0027] Fig. 7d shows a read transistor used to address the pixel, according to an embodiment.

[0028] Fig. 8a is a diagram showing how each one of 16 TG-SPAD subarrays can be triggered sequentially to be ON and OFF during different time windows, according to an embodiment.

[0029] Fig. 8b illustrates an array of TG-SPAD photodetectors in which each subarray is connected to a distinct counter, according to an embodiment.

[0030] Fig. 9 illustrates a modulated microring resonator (MRR) in an add-drop configuration, where the through and drop ports are connected to two TG-SPAD arrays, according to an embodiment.

[0031] Fig. 10 illustrates an electro-optical architecture for performing dot products using at least one TG-SPAD array, according to an embodiment.

[0032] Fig. 11 is a schematic of a photonic neural network based on arrays of TG-SPADs, according to an embodiment.

[0033] Fig. 12 is a simplified block diagram of a SPAD-based optical computing system, according to an embodiment.

[0034] Fig. 13 illustrates the main nonlinearities that can affect the performance of a silicon microring modulator, according to an embodiment. [0035] Fig. 14a illustrates how a photodiode (PD) can be interfaced with other electronic circuits, according to prior art.

[0036] Fig. 14b illustrates a single-photon avalanche diode (SPAD) frontend circuitry, according to an embodiment.

[0037] It will be noted that throughout the appended drawings, like features are identified by like reference numerals.

DETAILED DESCRIPTION

[0038] In embodiments, issues involved in the physical implementation of neuromorphic computing can be resolved with an efficient integration of well-defined photonic neurons and neural interconnects on a common electro-photonic platform, and in particular with the introduction of single-photon avalanche diodes (SPAD) as photodetectors in the systems, especially in an array configuration.

[0039] In optical computing and in general, a photodetector can act as an optical-to-electronic (O/E) converter to detect incoming photons and produce a change in current or resistance that is proportional to an input optical power. In the case of a photoelectric effect occurring in a PN junction, the absorbed incoming photons create free electron-hole pairs that drift across the junction, resulting in a power-dependent current, referred to as a photocurrent.

[0040] In addition to photodetectors, the interfacing of optical components with electronics can be facilitated with the use of mixed-signal integrated circuit blocks such as digital-to- analog converters (DACs) and analog-to-digital converters (ADCs).

[0041] The integration of an improved photodetector, able to detect individual photons, can lead to significant improvements in the performance of optical computing systems, and reduce the complexity of electronics. [0042] Neuromorphic photonic systems can exhibit high efficiency, high interconnectivity and high information density, and can pave the way to ultrafast, power efficient, low cost, and complex signal processing. Computations that are essential for neuromorphic computing include dot products, which are similar to multiply-accumulate (MAC) operations and convolutions, and electro-optical architectures can be utilized to perform these at a much higher frequency than with conventional electronics. Some of these architectures can successfully exploit novel neuroscientific tools, such as for instance, a silicon-photonics- based broadcast-and-weight architecture. Integrated with silicon photonics, these architectures have the potential to outperform conventional computing hardware. The four following electro-optical systems, corresponding to Figs la, lb, 2a, and 2b, are four neuromorphic architectures that can be improved with the use of an improved photodetector such as a SPAD, especially when used in arrays according to embodiments.

[0043] A design for an optical neuron based on a silicon photonics modulator, can consist of a balanced photodetector directly connected to a modulated microring resonator (modulated MRR). This optical neuron possesses the necessary capabilities of a network-compatible neuron: fan-in, high-gain optical-to-optical nonlinearity, and indefinite cascadability properties. For neuromorphic optical computing, a modulated MRR can be considered to be an electronic-to-optical (E/O) converter. A wide variety of effects can be considered for modulating a voltage- or current-dependent optical transmission, including thermo-optic, acousto-optic, electro-optic, and other effects, but in all cases, a modulator with an electronic control consists of an optical input, acting as a pump, which typically has a constant power and a constant wavelength. In the case of a voltage-mode power modulator, the optical transmission of the modulator is voltage-dependent.

[0044] Fig. la illustrates both a physical 102 and an electrical diagram 104 for an electro- optical architecture of a balanced photodiode 106 directly connected to an MRR modulator 108. The balanced photodiode 106 is biased 110 and converts impinging light into photocurrents. The photocurrents are combined 112 with a bias current 114 and their sum affects the refractive index of the MRR modulator 108. A pump signal 116 transmitting through the MRR is therefore modulated as an output light signal 118. [0045] Another configuration for an optical neuron based on a silicon photonics modulator is referred to as a double waveguide configuration, or an add-drop MRR configuration. In this case, the relationship between the transfer functions of a through port’s and a drop port’s light intensity, with respect to the input light, can be computed by interfacing the through and drop ports of a MRR into a balanced photodetector and an amplifier, typically a transimpedance amplifier (TIA). A user-defined modulation at the output can be achieved, because of the tunable gain of the TIA. The main purpose of incorporating a balanced photodetector at the output of an add-drop MRR is to represent positive and negative kernel values in analog photonics. A balanced photodetector can be used as an input port in order to allow for a push- pull current configuration. In the case of a spiking neural network, the resulting difference in currents from both photodetectors can flow directly into the gain section of a distributed feedback (DFB) laser.

[0046] Fig. lb illustrates a double waveguide configuration, also referred to as an add-drop MRR configuration, and how it can act as a photonic neuron with an input optical signal that can be modulated. The input light 120 is split in two parts. One part goes through a waveguide referred as a through port 122, which goes directly to a balanced photodetector 124. And the other part is transferred to a MRR 126, which modulates the signal and drops it to another waveguide, referred as a drop port 128, that is connected to the balanced photodetector 124. The electrical output signal of the balanced photodetector is then guided to a TIA 130 to be amplified.

[0047] The “broadcast- and- weight” protocol is one that’s been proposed as a standard protocol for implementing neuromorphic processors using integrated silicon photonic devices. It is based on a silicon photonic modulator and showcases the necessary capabilities of a network-compatible neuron. It can effectively emulate physical neurons, and act as a basic building block for neuromorphic processors. The broadcast-and-weight protocol is capable of implementing generalized, fully programmable and recurrent neural network models. In the broadcast-and-weight protocol, the output of each neuron is assigned a unique wavelength carrier that is wavelength division multiplexed (WDM) and broadcasted. Incoming WDM signals are first weighted by continuous-valued filters acting as reconfigurable photonic weight banks. The outputs of the weight banks are then summed by detecting their total optical power. The architecture can be implemented using a bank of tunable silicon MRRs that emulate physical neurons by recreating on-chip synaptic weights. To model the synaptic-like connections of physical neurons, Mach-Zehnder interferometers (MZI) can also be used instead of MRRs in a similar configuration. Neuromorphic photonic processors join a class of photonic hardware accelerators designed to assist in acquisition, feature extraction, and storage of wideband waveforms. These accelerators can manipulate the spectro-temporal profile of a wideband signal, a task difficult to accomplish using analog electronics over a broad bandwidth and with low loss.

[0048] Fig. 2a is a diagram representing the broadcast-and-weight protocol. It illustrates configurable analog weights in a neuromorphic photonics broadcast-and-weight network. MRRs for different wavelengths are used together to make a tunable spectral filter 240, that can input a variety of signals 242, split them according to their wavelengths, and modulate each one independently according to an electrical modulation 244. The output signals are summed by an optical power detector 246, which can produce an electrical signal 248 to power a laser source acting as an E/O convertor 250. With a laser source of a different wavelength for each one of a series of tunable spectral filters, the laser outputs can be multiplexed 252 into a single beam 254, newly weighted, which can be sent to another neuron or back to the same one. In some embodiments, the power detector 246 includes at least one SPAD photodetector.

[0049] A fourth system, that can be used for matrix multiplication, is one where, after each one of two matrices has been converted into a vector, the vector components can be loaded using tunable MRRs. Each component of a first vector can be encoded as the intensity of wavelength-multiplexed signal, and each component of a second vector can be encoded as a weight modulating the signals in a MRRs. Each weighted MRR can modulate the intensity of a component of the first vector, thereby effectively causing a multiplication of the two components. The components of the two vectors can be linked by means of an optical waveguide. Once the multiplications for all the signals and weights have been performed, their accumulation (i.e. summation) can be executed by detecting the total power of all the wavelength channels. In order to represent the positive and negative weights in analog photonics, a balanced photodetector architecture can be incorporated at the output of the drop and through ports of the add-drop MRRs, and it can be followed by a TIA to provide a variable gain.

[0050] Fig. 2b illustrates an architecture for a photonic computing block, including matrix loading blocks. After input data 260 has been processed by a time-division multiplexing (TDM) unit 262, it can undergo photonic multiply-and-accumulate (MAC) operations in a photonic MAC bloc 264. In the MAC bloc, each wavelength of a wavelength-multiplexed signal 266 can be loaded to an independent MRR 268 via a silicon waveguide 270. Each component of a first vectorized matrix can go through a digital-to-analog (DAC) converter 272 and be loaded on an MRR 268 by tuning the MRR’s resonant wavelength to modulate the intensity of a corresponding wavelength of input signal 266. After the components of the first vectorized matrix are loaded, the components of a second matrix can be loaded similarly, to a second set of DACs 274, that tune a second set of MRRs 276 accordingly. Multiplication is performed when a signal weighted with a component from a first vector 278, is modulated by an MRR weighted by a second component 276. The multiplications of components are accumulated (i.e. summed) by a balanced photodetector 280 and the result can be amplified by a TIA 282. The result can then be converted to a digital signal by an ADC 284, and undergo further processing with digital electronics hardware 286. With a sufficiently elaborate photonic bloc 264, an at least 512-size vector multiplication can be computed 288. In some embodiments, the accumulation part of a multiply-and-accumulate operation is performed using at least one SPAD photodetector.

[0051] The limitations of neuron-emulating electro-optical architectures performing vector dot products can be avoided by biasing their summation photodetector (PD) above the breakdown voltage and having it operate in Geiger-mode as a single-photon avalanche diode (SPAD) photodetector. When operated in Geiger-mode, a single incoming photon can trigger a self-sustaining avalanche event and thus easily be detected, making a SPAD a remarkable sensor for low intensity light detection. SPAD-based systems can provide significantly improved single-photon detection sensitivity, as compared with conventional photodiodes. Owing to their simple structure, SPADs can be integrated into application-specific integrated circuits (ASIC), for a wide range of applications such as intra-chip communications, quantum key distribution, deep space laser communications, three-dimensional imaging and charged particle detection.

[0052] A SPAD is a semiconductor device that is able to acquire light signals down to the single-photon level with a high temporal resolution, extremely low noise, and extended Dynamic Range (DR). SPAD photodetectors are interesting because of their good photon detection efficiency (PDE) and their low timing jitter.

[0053] One of the major issues to overcome, for the realization of an efficient physical implementation of neuromorphic computing, is the error arising from inherent noises such as stochastic shot noise, spectral noise, Johnson-Nyquist noise and flicker noises. Main noise contributions are the quantization noise in an ADC, and distortion from the radio-frequency (RF) signals applied to the modulators. The development of radio-frequency (RF) complimentary metal-oxide semiconductor (CMOS) integrated microelectronics chip, including high-speed drivers, control circuitry, DACs, ADCs, synchronous dynamic random- access memory (SDRAM), and 3D integration with the silicon-photonic platform can help to minimize the parasitic effects on the overall throughput of the system.

[0054] The conversion quality of a system’s photodetector (PD), which generates an output electrical signal from incoming optical signal, can greatly affect the overall performance of an entire system. In general, an ideal PD should possess features such as high responsivity, large bandwidth, high quantum efficiency (QE), low applied voltage-bias requirements, low dark currents, and compatibility with CMOS. Unfortunately, a PD creates a gain-dependent excess noise source, which limits the maximum gain to between 2 and 20. A disadvantage is that a PD has to be interfaced with high bandwidth analog electronic circuits, such as a TIA and an ADC. These analog peripheral circuits can consume a significant amount of power, which has a detrimental effect on the performance of an optical system comprising numerous PDs. Embodiments address these issues with the use of a time-gated single-photon avalanche diode array (TG-SPAD) architecture, which can easily be integrated with a CMOS process and achieve good noise immunity, low power dissipation, high packing density, and scalability. [0055] In embodiments, the basic building block of neuromorphic photonics is a photonic neuron, which is an optical-in, optical-out device. It can use an optical/electrical/optical (O/E/O) signal pathway with a lumped, intermediate electronic connection, to convert multiple independently weighted inputs, into a single output, to apply a nonlinear transfer function to the weighted sum of the inputs, and to produce an output capable of driving multiple other neurons, including itself. In embodiments, a photodetector utilized in the optical-to-electrical conversion can be a reverse-biased PN (p-n junction) photodiode. In the case of a spiking neural network, the current resulting from a photodetector flows directly into the gain section of a DFB laser, for optical conversion. In other approaches, such as the “broadcast-and-weight” approach, an electrically weighted sum can modulate the corresponding wavelength-division multiplexing (WDM) carrier through a nonlinear or dynamic electro-optical process by means of MRRs or MZIs. At the output of the photodiode, the current can be amplified by means of a TIA which, in the case of a monolithic integration, can be fabricated on the same chip. For heterogeneous integration, the TIA and other electronic control circuitry can be fabricated with other standard CMOS processes, and be interfaced with a corresponding photonic chip by means of wire-bonding or flip-chip bonding. In certain cases, such as with a matrix multiplier, interfacing with an ADC is also required, to compute the digital representation of the data.

[0056] Embodiments involve and include the use of a neuromorphic electro-optical system, based on an array of time-gated single-photon avalanche diode (SPADs) photodetectors, to accelerate signal processing, and to decrease the use of analog design blocks. Because the output of a SPAD is already in the digital domain, no additional analog design blocks are required for further processing. This can provide significant advantages in terms of lower power consumption, higher computational efficiency, higher noise margins, higher speed operation and minimized capacitive loading.

[0057] In an embodiment, a time-gated SPAD (TG-SPAD) architecture is introduced to improve the dynamic range and count rate (i.e. throughput) of a photodetector. Typically, the count rate or the frequency of operation of a single-photon detector is limited by its inherent dead time. In an embodiment however, the count rate can be increased significantly, and the effect of the dead time of the photodetector can be mitigated. [0058] A single-photon avalanche diode (SPAD) is a semiconductor device able to receive and acquire light signals down to the single-photon level with a high temporal resolution, an extremely low noise and an extended Dynamic Range (DR). As such, a SPAD is a device that can be used for detecting an optical input signal. The fundamental difference between a SPAD and a photodiode (PD) is that a SPAD is specifically designed to operate with a reverse bias voltage well above the breakdown voltage (V _BD ). In contrast, a PD operates at a bias voltage that is less than the breakdown voltage. For detecting incident radiation, a SPAD exploits the photon-triggered avalanche current of a p-n junction, reverse-biased at a voltage signal higher than V _BD , by a so-called “excess bias”. With such a bias voltage signal, the electric field is sufficient that a single charge carrier, injected in the depletion layer, can trigger a self-sustaining avalanche. In some embodiments the electric field is greater than 3E5 V/cm. The current rises swiftly (with a sub-nanosecond rise time) to a macroscopic steady level, in the milliampere range. If the primary carrier is photo-generated, the leading edge of the avalanche pulse marks the arrival time of the detected photon (with picosecond time jitter). The current continues to flow until the avalanche is quenched by lowering the bias voltage down to, or below V _BD · This lowers the electric field across the junction, thus ceasing the current, by disabling the acceleration of the carriers and preventing their impact with lattice atoms from ionizing them. In order to detect another photon, the bias voltage must be raised again above V _BD · Ignitions due to carriers generated by thermal or tunneling processes represent the photodetector’s own noise, and cause a so-called dark count rate (DCR). Moreover, some carriers also get trapped during an avalanche, and are released later when the SPAD is ready to detect a subsequent photon, thus causing spurious ignitions called after- pulses. Suitable circuits, possibly tailored on fine modeling of the electrical behavior of such photodetectors, can be employed together with the SPAD, in order to achieve the best timing performance and to lower the after-pulsing effect. In addition, a SPAD can be turned ON and OFF by analog modulation of its bias voltage (a few volts), from below V _BD to above V _BD · The ON and OFF states of a SPAD can be referred to as “activated” and “deactivated” states, and the actions of turning a SPAD ON and OFF can comprise applying and removing a bias voltage to the SPAD. The application and removal of a bias voltage to a SPAD can also be referred to as “activating” and “deactivating” the SPAD, and such a bias voltage can be applied as a voltage signal. A photon that is absorbed when the photodetector is biased below V _BD does not trigger a self-sustaining avalanche; hence it is not detected by the read-out electronics. A SPAD requires a suitable circuit, which has to: 1. sense the leading edge of the avalanche current; 2. generate a standard output pulse synchronous with the avalanche build up; 3. quench the avalanche current by lowering the bias voltage down to the breakdown voltage V _BD ; and 4. restore the SPAD to an operative level. The related circuitry can be referred to as a quenching and processing circuit.

[0059] Fig. 3 is a block diagram of a SPAD photodetector counting module, according to an embodiment. When photons 310 are incident upon a SPAD photodetector 320 that is biased at an operating bias voltage signal V _op 330, an avalanche current process is initiated. The avalanche current flows through a ballast resistor R 340, initiating a passive quenching process which soon senses the avalanche current. This in turn starts an active quenching process by closing switch S _Q 350 (Quenching switch), which rapidly discharges the SPAD photodetector’s capacitance C _d 360 with a time constant R(S _Q )xC _d , where R(S _Q ) represents the nominal on-resistance of switch S _Q 350, and C _d represents the SPAD’s terminal capacitance 360. Using this technique, it is possible to keep the SPAD in a quenched state for a definite period of time, referred to as a hold-off time. To recharge and restore the SPAD’s bias voltage 330, switch S _Q 350 can be opened and switch S _R (recharge switch) 370 closed in quick succession. This can lead to a quick recharge of the SPAD with a time constant given by R(S _R )xC , R(S _R ) being the on-resistance of switch S _R 370. After a few nanoseconds, switch S _R 370 is opened again, ending the recharge phase and making the SPAD ready for another detection event. A Control Logic module 380 can be used to open and close switches S _Q 350 and S _R 370, and a counter 390 can keep track of the switching. A benefit of the SPAD architecture is the SPAD photodetector’s direct integration. This can replace the use of discrete components and provide a well-defined delay. It can also speed up the voltage- defined dead time and result in a much-reduced parasitic capacitance, and a smaller avalanche charge, which can consequently reduce the intervention reset.

[0060] The maximum count rate and bandwidth of a SPAD can be limited by an inherent RC (resistance capacitance) time-constant, which can affect the recharge time of the SPAD. In order to address this issue, embodiments include an array of time-gated SPADs. [0061] In embodiments, an advantage of using a SPAD is that it can be turned ON and OFF, or activated and deactivated, by biasing its photodiode above a breakdown voltage V _BD during a very short period of time, and then removing the bias voltage. The actions of activating and deactivating a SPAD can be referred to as time-gating, and the activation of a SPAD for a specified time-window can be referred to as a SPAD’s duration of activation. The time gate can be also adjustable in width (i.e. “width” and “window” being terms of the art meaning “duration”) and in frequency (i.e. repetition rate, or number of activations per unit of time), as it can be repeated periodically, with respect to a trigger frequency (i.e. a synchronization pulse), which can be provided by an integrated voltage-controlled oscillator. A feature of such embodiments is that the SPAD photodetector is sensitive only during the time gates when it is activated, and will not detect any photon in the absence of a gate signal, i.e. when it is deactivated.

[0062] Fig. 4a illustrates, according to an embodiment, an implementation of a time-gated SPAD, where a train of periodically time-gated pulses 410 are generated. The duration 420 of each pulse 420 and the delay 430 between each pulse can be controlled with a bias voltage signal. With such a pulse train, the SPAD is sensitive to detect photons when the bias voltage signal is applied 440, and insentitive even if a photon is incident 450, when the bias votage signal is absent.

[0063] In embodiments, when an avalanche process is triggered due to an incoming photon within the time gate, a pulse of adjustable width is generated at the output of the detection electronics, and a user-tunable dead-time can substantially simultaneously be initiated by the quenching circuitry. (Events occur substantially simultaneously when they occur at exactly the same time or nearly so.) The application of a suitable dead-time, in combination with the time-gating feature, can be exploited to drastically reduce the effects of a dark count rate (DCR) and after-pulsing.

[0064] Fig. 4b illustrates how a time-gated signal can be generated, according to an embodiment. A synchronization pulse, generated by a voltage-controlled oscillator (VCO) 460, is delayed to turn ON (i.e. activate) the SPAD after a specified time window. Using a variable delay block 470, the amount of delay can be user-tunable with a step delay of 10 ps. In order to select the width of the delayed gating window, a pulse width modulator 480 can provide a suitable ON -time to the SPAD photodetector. The width of a time-window can be chosen to be from 1 nanosecond (ns) to 2 ns, determining the time frame during which the SPAD photodetector should remain active and ready for photon detection.

[0065] In an embodiment, a SPAD array architecture can be made of SPADs each having a maximum count rate of 1/T _dead , where T _dead is the SPAD’s OFF-time, also referred to as the SPAD’s “dead time”, or its duration of deactivation. Each subarray (SA) can consist of many time-gated SPADs (TG-SPAD) and any number ST of the many SPADs can be activated during a same time-window AT. The activation of the many SPADs of a same SA can be substantially simultaneous, and so can their deactivation. In an embodiment, each sub-array (SA) can consist of 16 TG-SPADs disposed of in a square of R = 4 rows and R = 4 columns, and in another embodiment, it can consist of 64 TG-SPADs disposed of in a square of R = 8 rows and R = 8 columns. However, other array configurations and other numbers of rows and columns can also be different. Activating all the SPADs of a SA substantially simultaneously and during a same time-window can increase the count-rate of the SA to R ² /T _dead , where R ² is the number of pixels (i.e. rows x columns) in the SA. Thus, dividing a large SPAD array into smaller groups of M x N subarrays SA can enable each SA to effectively function as though it was an individual SPAD (M and N being the numbers of rows and columns respectively, of an array of SPAD subarrays), and it can increase the effective count rate of the SPAD array architecture to M x N x R ² /T _dead ·

[0066] Fig. 5 illustrates a TG-SPAD array architecture allowing an enhanced speed of operation, dynamic range and count rate, according to an embodiment. During a defined time-window AT, each SPAD 510 can make a detection count 520 of 0 or 1. The count rate 530 of a SPAD is and is determined by how long (T _dead ) the SPAD is unbiased (i.e.

OFF-time or deactivation duration). A subarray (SA) 540 of SPADs can include R = 8 columns of SPADs, by R = 8 rows of SPADs, resulting in a square of R x R = 64 SPADs. For such a SA, the count rate 550 is If many subarrays are combined into greater square of

M rows of subarrays and N columns of subarrays, the count rate of the entire array 560 can be . In the embodiment of Fig. 5, the array includes M = 4 rows and N = 4 columns of subarrays.

[0067] In an embodiment, the architecture of a SA is such that each SA can be triggered at a same, specified time, and for a same time window, and it can have its own dedicated counter (that is, a counter allotted for this particular SA) to register its photon count. All the SPADs of a SA can be activated substantially simultaneously, and after a time window has passed, they can also be deactivated substantially simultaneously.

[0068] Fig. 6 illustrates a subarray (SA) architecture consisting of 16 SPADs, each of which can be referred to as a pixel, and frontend circuitry. Time-gating buffers 610 can turn the SPADs on and off independently according to pre-defmed OFF-time delays and ON-time windows. The time gated SPADs 620 can be arranged in a subarray (SA) of 4 columns and 4 rows to make a 16-SPAD SA. Each SPAD has a dedicated mixed quenching circuit (MQC) 630. The counts for all the SAs can then be summed in a counter 640 and stored in a memory 650, such as anon-transient memory.

[0069] Fig. 7a, Fig. 7b, Fig. 7c, and Fig. 7d represent frontend circuitry of a TG-SPAD that is part of a subarray of SPADs, according to an embodiment.

[0070] In Fig. 7a, a voltage signal of operation V _OP 705 is applied to photodetector 710. The voltage signal of operation V _OP 705 is greater than the photodetector’s breakdown voltage V _BD 715 and it can be applied for a short period of time. The difference between the applied Vop 705 and the photodetector’s breakdown voltage V _BD 715 can be called the excess bias voltage V _EX 720. The photodetector 710 is only sensitive and able to detect incoming photons during this adjustable time period, which can be referred to as a time-gate. In the first part of the circuit, the time-gating operation is performed by means of a p-channel metal oxide (PMOS) transistor M _G 725, which can pull the SPAD anode voltage up to an intermediate supply voltage V _OP above the diode breakdown voltage V _BD , essentially being the excess bias voltage V _EX = V _OP - V _BD of the SPAD. The time-gate circuit can make use of thick oxide transistors M _G 725 for time-gating, for quenching and for reset operation M _R 730. t a Sea An w perio cneaucdnseo [ cld0yaw bi0nen7 s wg a4u oci]cctt aihh Icvcnu ttahir tt avheanaetd sltecltu e neiy finmbo dfdootisne,reb sta edai aocman odt t sctifiiupivhmmalea ad p rm,er ieientcee t trihdam 8 t siatwu7nete1bdgo. a4an4 ir A S Sn3r aAdA8asc4yestP of,i civnC ana aeanTrnittedn0dteie Sio1t bslvi t tA aynselrhatite s cg aet i tango pshdnderp,ero ap b ue acc see ea decnete redeodipuce basalty f dyetoeed a.ladl T uoc c ahstowineeuveryna. Sdtt nAee burdys,m, sl c atble hu eaiyseaoa dbn,rcvnse s ahtiai oanm cscfn oagt su titnneiiv almealt ba isrte arnedd b e inaech t ari rg peghseoprteeocdntrinv o c tenoh beeuen a ot rfetth cgeea s tslri da isennttotseericns Mtts [ ceoi0odt _B ry0u M b 77n i4y1nt _C e0]f aro 7 In. ar3nrm T S5e FhaA u aiet ogoinsi tcfo c n.hexdkandu 7ei pdn ambh o oe,o tx gpbh at tiiteroidvinar tcneehn-a iefDi tch aen tiom idn t aeetone. wdn dsei tinthtedyu 1cost9 iwn t ehf.aeo Tcorrn vmhrho c tehaa al ctetnoai soug Sp gnnePeitvAc oe f ien t we ninsid mtyoewt fhosor ad ncuc oomf r redeehriconceouugr ostdipv citneoigcn tais tlm intouhonnantne o dcrfee it t t [mhe to0hcep0et al7o Sne pr2Pme e] aArmerf IrnDnobatryoe Fm fddir aag sio a nsm g bin.nneryc a 1te 7gexee-nclatnbet,t odi slft t cy peha ich a ces entoo at 7i5n 0g , M a w tn ₁ rdah cno aaslnie ss.e ctotaru o sf Me i ₁ n5 tshv57iees.4tr A5ote,rcr t Mtsriav 7 ₂ n n d M ₂ c laatnc h b e to u fsleipd f tesroeo ct rmoe sust ineattttsee t rrh ae. w aicntgiv haot [ew0d0 e7 ina5c] she Fq SiugAe. n 8c cgccaareean i,smss bi aev s deh sliouya nfr oftte,f r o e refaenca tthhd [ o tei0 Sr tmr p0A tai7renxi3g 8s we]ig1lsi Oe0 fntrordn ceoroadn F Mwnti timeto dgs f b _R n. cuo.b _D e bdo Iru 7oeinnr cddnts Oii, aghrimns tcNh d ptues eie,a ehcwoe fnno p,dlli dxo (eew a 7nlpc.6seet)d0 Tniv,dh 8a b wie2tnye0hg cd,io ac ol th ounh drmeo ie ts 1n a pah Ond aude u ncNd cl lsltiaareeinenvndd fesoaos tts d i broise to ut _O i ppm _W e t _N reriao 7n cd6as t l0iainm os,ttcf wo beh/re 1hd. si5etl aaeact ncte Mstiiv tv _U ha 8ne ea _P rt3s aatoeii 70 oscduos6,rht agno5h a O pr On t au ti MFdcNrmlatFls- _D oc tuisv a StiAo inm is omf dee adaic satutiebvlaayrt tnerh 8aday a4,t0 s p tuhr wceehvh aie [0076] Fig. 8b is a schematic of how the counters for each SA of an array of SAs, can be read sequentially, and can provide optical intensity data for a wide time scale, making the architecture of an embodiment suitable for high frequency applications. Each SA 810 can be associated with a dedicated counter 820, and the SAs can be turned on sequentially 830 during consecutive time windows.

[0077] Because after each detection event, a deactivation or dead time can be applied to a SPAD, a drawback of a SPAD can be a low count rate, and this can limit the applications of SPADs in optical computing. However, using the technique of an embodiment, the problem of a low count rate can be resolved. The time-gate can be generated on-chip by means of a voltage-controlled oscillator (VCO). The output of the VCO can be interfaced with a variable delay generator applying a user-tunable delay to select the time instant at which the SPAD needs to be turned on. In order to provide a variable activation or ON -time to the photodetector, the output of the variable delay generator can then go through a pulse width modulator and then to a level-shifter to provide a suitable excess bias voltage to the SPAD.

[0078] In embodiments, an array of TG-SPADs can be used to collect the through port and drop port outputs of a modulated MRR in an add-drop configuration. This architecture offers significant improvement over conventional computing units used for processing signals in optical computing systems. A feature of this architecture is that the dark count rates (DCR), inherent to each SPAD photodetector, can be cancelled out at the output by means of a subtractor.

[0079] Fig. 9 shows how two TG-SPAD arrays can be used with a modulated MRR in an add-drop configuration. The MRR’s drop port output 910 and through port output 920 are connected to two TG-SPAD arrays 930. Each one of the two arrays collects an output from the MRR, and the two outputs are combined by a subtractor, producing the system’s final output.

[0080] To perform a dot product with low-intensity signals according to an embodiment, a TG-SPAD array system can be incorporated at the output of the drop and through ports of a series of micro-ring resonator (MRR) weight banks. Each component of a first input vector V ₁ can be encoded as a signal intensity having a distinct wavelength, the intensity of each signal corresponding to a vector component. Each component of a second input vector V ₂ can be encoded as a weighing factor tuning the resonance wavelength of a MRR. As such, each multiplication of a dot product between V ₁ and V ₂ is performed when a V ₁ signal is weighted by a V ₂ weighing factor tuning a MRR to modulate the V ₁ component wavelength. Such tuning can be performed by heating each MRR independently to different temperatures, but other mechanisms are possible, including thermo-optic, acousto-optic, electro-optic, and other mechanisms. A photodetector collecting all the products can then perform the sum of the V ₁ V ₂ dot product. If, according to embodiments, the photodetector is based on TG- SPAD arrays, the signal intensities can be very low.

[0081] Fig. 10 shows an electro-optical architecture that can perform a dot product. A pair of TG-SPAD arrays 1010 can be incorporated at the output of the drop and through ports 1020 of a series of MRRs 1030, each of which corresponding to a distinct vector component multiplication. A ₁ to A _k are components of a first vector, encoded as intensities 1040 of different wavelengths. They are multiplexed by a wavelength-division multiplexer (WDM) 1050, and an optical waveguide 1060, such as silicon, links them to the MRRs 1030, which are modulated by weight banks F ₁ to F 1070. Weight banks F ₁ to F _k 1070 are filter values modulating the MRRs 1030 according to components of a second vector. In embodiments, a weight bank is implemented as an independent heater, modulating a MRR by tuning its temperature and consequently its wavelength of resonance. The tuning is effectively a multiplication operation between a component of a first vector, encoded as a signal intensity in the MRR, and a component of a second vector, encoded as the MRR’s temperature and wavelength of resonance (i.e. “tuning frequency”). Each MRR is therefore the site of a product calculation between two vector components. The products, each having a different wavelength, are then summed in two TG-SPAD arrays 1010. A subtractor at the output of the two TG-SPAD arrays can cancel out the dark noise and a register can then provide electronic gain to the output.

[0082] In an embodiment, an optical computing system performing a plurality of dot products can be implemented using an array of TG-SPADs, and the implementation accomplishes better performance in terms of computational efficiency, bandwidth, and power consumption. [0083] Fig. 11 is a schematic of a photonic neural network based on arrays of TG-SPADs, wherein the outputs of many dot products are used to modulate the output of as many laser diodes, having as many distinct wavelengths, and the modulated laser diode signals are multiplexed into a single output waveguide, such as silicon. A series of tunable spectral fdters, such as MRRs 1010, using a series of weight banks 1020, which in some embodiments can be independent heaters, realize independent weighting functions for the input signal 1030 of each TG-SPAD array 1040. The total optical power of each spectrally weighted signal 1030 yields an electronic sum 1050 of the input channels 1030 to the TG-SPAD arrays. The electronic sum 1050 is then transduced, using a laser diode source 1060 and an optical modulator 1070, into an optical signal 1080.

[0084] In embodiments, the interfacing of a MRR with electronics can be facilitated with the use of a digital-to-analog converter (DAC), while the storage of outputs and retrieving of inputs can be achieved by means of at least one digital memory. The memory, which can also store photon counts accumulated by integrated counters, can be interfaced with a computer, where information is already in a digital representation.

[0085] Fig. 12 is a simplified block diagram of a SPAD-based optical computing system, where the interfacing of a MRR 1210 with electronics is facilitated with a DAC 1220, while the storage of outputs and retrieving of inputs can be achieved by means of a digital memory 1230, which can be non-transient. The memory, which can also store photon counts accumulated by at least one integrated counter 1240, can be interfaced with a computer, where information is already in a digital representation.

[0086] In embodiments of a neuromorphic photonic network, the power of a laser at a modulator neuron’s output can be sufficient to drive subsequent neurons of a same network. In a neuron design, a signal’s cascadability is a factor that should be considered for the signal to be able to evoke at least an equivalent small-signal response after one round-trip, if fed back to its originating neuron. If the cascadability condition is not satisfied, a signal will eventually attenuate over time. [0087] A modulator-based, broadcast-and-weight system, as shown in Fig. 1c, can be fragmented into modulator components 144 and receiver components 146. Because the input optical power generates a photocurrent, the receiver’s impedance R _r determines the conversion quality. The bandwidth ƒ can be determined with equation where C _mod is the modulator’s PN junction capacitance. Hence, an increase in R _r causes a decrease in bandwidth ƒ

[0088] For a reverse-biased, voltage-mode, MRR depletion modulator, is the modulator’s (i.e. the voltage required to shift the MRR’s resonance wavelength from one half- wavelength), and R _PD is the photodetector’s responsivity. A modulator’s pump power P _pump can be calculated using the following equation: which by inserting equation inverted for R _r , becomes:

The photodetector’s responsivity is defined as the average photocurrent produced per unit optical power, and it is given by: where I _p is the measured photocurrent and P _op is the incident optical power at a particular wavelength oƒer the sensor area.

[0089] For an MRR depletion modulator, fabricated in a typical silicon photonic foundry platform, = 1.5 V and C _mod =35 fF. A typical value for a photodetector PD’s responsivity on the same platform is RPD = 0.97A/W. Hence, for a given signal bandwidth, the minimum pump power for a modulator can be calculated as 2. 16 x 10 ^-13 W/Hz. In contrast, the responsivity of a SPAD is much higher as compared to a PD’s, by an order of about 10E+5. This minimizes the minimum required pump power to about 2.2x10 ^-17 W/Hz.

[0090] Ring modulators systems, such as microring and microdisk resonators, can be quite complex and challenging to design, due to their narrow-band nature, which makes them highly sensitive to fabrication variations and environmental fluctuations, such as substrate temperature. In addition, the small size and high Q factor (quality factor) of these structures can lead to electric field enhancement and strong light confinement. These attributes can give rise to optical power densities that are high enough to generate nonlinear effects, including thermal and carrier-induced optical bi-stabilities. Even with moderate input optical powers (on the order of milliwatts), the nonlinear effects can result in unwanted behavior.

[0091] Nonlinearities affecting performance essentially include: free carrier dispersion and free carrier absorption (FCA), both affecting free carrier density, two-photon absorption (TP A), and thermal effects. These factors can affect the power handling limits in silicon microring modulators. Presently, developments of longer link distances and improved link budgets require an increase in input optical powers, which can further aggravate the issues associated with the handling of high powers, particularly in resonance modulators. Because SPADs have a very high responsivity and can detect very faint optical signals even at the single-photon level, the implementation of SPADs can help mitigating the nonlinear effects, simply by minimizing the input optical power required for a system.

[0092] Fig. 13 is a time domain model for an externally modulated silicon resonator, showing the main nonlinearities that can affect the performance of a silicon ring modulator. Ideal control would involve applying a modulation signal 1310 to cause a resonance shift 1320. However, the resonator’s optical energy 1330 can be sufficiently dense to cause two-photon absorption 1340, which in turn can cause increased free carrier density 1350 and self-heating 1360 in the resonator, both of which can further affect the resonance shift 1320. Two-photon absorption 1340 can affect not only the production of free carriers 1350 but also their loss rate 1370. Essentially, the main nonlinearities affecting performance are: free carrier dispersion and free carrier absorption (FCA), both affecting free carrier density 1350, two- photon absorption (TP A) 1340 and thermal effects 1360. [0093] In embodiments, the latency time of an electro-optical conversion is the time delay between the beginning of a signal acquisition, and the time when data is available at the output of the converter. The latency time can also be referred to as a “settling time”. It cannot be zero and is typically viewed as the time delay required for an ideal step input to converge, within an error margin, to a final digital output value. The latency time can be critical in neuromorphic and optical computing applications.

[0094] Fig. 14a illustrates how a photodetector (PD) 1410 can be interfaced with other electronic circuits, first to a TIA 1420, and then from the TIA 1420 to an ADC 1430. In an embodiment, the following is a typical latency time Δt _L calculation, using typical values for the electronic circuits used. First, the latency time of a TIA 1420 Δt _{L TIA} can be obtained by summing those of its submodules: a gain stage, and a buffer:

Then, the latency time of an ADC 1430 Δt _{L ADC} can be similarly obtained, its submodules being a comparator, an encoder and an amplifier:

The total latency time Δt _{L total} in the case of a PD system is then: [0095] Fig. 14b illustrates a SPAD’s 1440 frontend circuitry, which can include a buffer 1450 and a counter 1460. The latency time Δt _L of the frontend circuitry in the case of a SPAD system, using a typical value for a buffer Δt _{L Buffer} = 73 ps, and a typical value for a counter Δt _{L counter} = 73 ps, can be calculated as follows:

From the above comparison, using typical values, it can be inferred that the latency time performance of optical computing based on TG-SPAD arrays ( Δt _{L total} = 146 ps) is typically much better than that of a PD-based system ( Δt _{L total} = 359 ps).

[0096] According to embodiments, the implementation of a time-gated SPAD array for photonics can help mitigate the limited count rate and bandwidth of other SPAD implementations, and also resolve bottlenecks inherent in other neuromorphic architectures, including I/O interfacing with digital systems via DACs and ADCs, modulator pump power, non-linear effects, and latency time. A TG-SPAD array architecture with digital outputs can be used to perform basic convolution operations, including the dot product of two vectorized matrices, as well as variety of nonlinear optical-to-optical transfer functions that are relevant for a wide variety of neural processing tasks. It can also perform them with a significantly lower runtime and improved computational efficiency, as compared to neuromorphic systems not using TG-SPADs.

[0097] Embodiments include a method to employ at least one single photon detector in optical computing systems for complex and high-speed operations.

[0098] Embodiments include an architecture that can derive optical intensity by means of accumulated photon counts in a plurality of time bins, and eliminate the utilization of complex analog light intensity measurement systems. [0099] Embodiments include a time gated SPAD array architecture that is divided into several subarrays and where each subarray registers the optical intensity for a sequence of specific ON and OFF time slots. This technique can allow a performance improvement over using an individual photodetector, as it can record the optical intensity for numerous consecutive time windows.

[00100] Embodiments include a system architecture incorporating only simplified digital blocks (e.g., counter), instead of using high bandwidth analog electronic circuits.

[00101] Embodiments include a system architecture incorporating both simplified digital blocks (e.g., counter), and high-bandwidth analog electronic circuits.

[00102] Embodiments using the photonic filter bank architecture can be implemented to calculate inversion and multiplication operations for complex-valued matrices.

[00103] Embodiments can be employed in photonic computing technology to compute complex-valued matrix inversion and matrix multiplication for wireless-communication applications.

[00104] Embodiments can achieve improvements in terms of noise immunity, reduction in modulator pump power, nonlinearities and latency time, as compared with architectures not based on SPADs.

[00105] Embodiments can achieve improvements in dynamic range, count rate and in the reduction of dark noise, as compared with architectures not based on SPADs.

[00106] Embodiments include the adoption of single-photon photodetectors in a photonic neural network.

[00107] Embodiments can be used for improving the performance of optical computing systems in terms of power consumption and computational efficiency. [00108] Embodiments can be used in combination with SPADs having improved performance, especially where CMOS technology is concerned, and these can include Ge-on- Si SPADs, which can offer improved photon detection efficiency at higher wavelengths.

[00109] Embodiments can also be used in combination with superconducting nanowire single photon detectors (SNSPDs), which can offer gigacount-per-second count rate.

[00110] An aspect of the disclosure provides a method for detecting an optical input signal by receiving an optical signal by an optical detector array divided into a plurality of subarrays such that each subarray includes a plurality of optical detectors; activating the subarrays in sequence by applying a voltage signal to each optical detector of a subarray substantially simultaneously, while substantially simultaneously deactivating and leaving deactivated the optical detectors of other subarrays until a further iteration of the sequence; and recharging the deactivated optical detectors of the array. In an embodiment, each subarray can be connected to a dedicated counter and an output of each activated subarray can represent a photon count. In an embodiment, the photon count of each dedicated counter can be registered in a non-transient memory. In an embodiment, a time-gating sequence of activating and deactivating the subarrays of an array can be reiterated indefinitely and until stopped. In an embodiment, activating a subarray can comprise applying bias voltages to its optical detectors, and deactivating a subarray can comprise removing bias voltages from its optical detectors. In an embodiment, activating and deactivating a subarray can be performed by a voltage-controlled oscillator, a variable delay block, a pulse-width modulator, and a buffer. In an embodiment, each optical detector of an array can be a single-photon avalanche diode (SPAD). In an embodiment, each optical detector of the array can be a superconducting nanowire single photon detector (SNSPD).

[00111] An aspect of the disclosure provides a system for performing optical computations that can include at least one optical waveguide for propagating an optical input signal; at least one row of at least one optical element, each optical element modulated by an electrical input signal and each optical element for producing a correspondingly modulated optical output signal from the optical input signal; and at least one single-photon avalanche diode (SPAD) for receiving the optical output signal modulated by the at least one optical element. In an embodiment, a system can include a plurality of SPADs, configured as a SPAD array for receiving an optical output signal; the SPAD array can be divided into a plurality of SPAD subarrays such that each SPAD subarray includes at least one SPAD, and each SPAD subarray can be connected to timing-gating circuitry for activating and deactivating the SPAD subarrays, one at a time in sequence; and each SPAD subarray can be connected to a dedicated counter. In an embodiment, a system can include at least one SPAD that can be time-gated according to parameters including a SPAD activation duration, a SPAD deactivation duration, and a rate at which activation and deactivation can occur; a SPAD activation allowing its operation, and a deactivation allowing its recharge. In an embodiment, each optical element of a system for performing optical computations can be a modulated microring resonator (MRR) having a drop port for transmitting an optical signal to a first SPAD array, and a through port for transmitting an optical signal to a second SPAD array; and the outputs from the first and second SPAD arrays can be received by a same subtractor. In an embodiment, an optical element of a system for performing optical computations has a drop port and a through port, and the outputs from each row of optical elements can be received, through a first and second arrays of SPADs, by a respective subtractor. In an embodiment, a laser source can be connected to each subtractor collecting the output of a row of optical elements through SPAD arrays, such that each laser source can be modulated by the output of a subtractor. In an embodiment, at least one laser source is modulated by the output of a subtractor, and a wavelength division multiplexer (WDM) can receive optical signals from each modulated laser source and multiplex the optical signals into a single output.

[00112] Embodiments have been described above in conjunctions with aspects of the present invention upon which they can be implemented. Those skilled in the art will appreciate that embodiments may be implemented in conjunction with the aspect with which they are described, but may also be implemented with other embodiments of that aspect. When embodiments are mutually exclusive, or are otherwise incompatible with each other, it will be apparent to those skilled in the art. Some embodiments may be described in relation to one aspect, but may also be applicable to other aspects, as will be apparent to those of skill in the art. [00113] Although the present invention has been described with reference to specific features and embodiments thereof, it is evident that various modifications and combinations can be made thereto without departing from the invention. The specification and drawings are, accordingly, to be regarded simply as an illustration of the invention as defined by the appended claims, and are contemplated to cover any and all modifications, variations, combinations or equivalents that fall within the scope of the present invention.