Title:
METHODS AND APPARATUS FOR BIPOLAR ELIMINATION IN SILICON-ON-INSULATOR (SOI) DOMINO CIRCUITS
Document Type and Number:
WIPO Patent Application WO2000055971
Kind Code:
A8
Abstract:
In brief, methods and apparatus are provided for bipolar elimination in silicon-on-insulator (SOI) domino circuits. The apparatus for bipolar elimination in silicon-on-insulator (SOI) domino circuit includes a domino silicon-on-insulator (SOI) field effect transistor (402). An input is coupled to the domino silicon-on-insulator (SOI) field effect transistor (402). A predischarging device is coupled to said domino silicon-on-insulator (SOI) field effect transistor (402). The predischarging device is activated during a precharge mode of the domino circuit, so that the SOI parasitic bipolar transistor is not activated. A dynamic input circuit (300) couples the input to the domino silicon-on-insulator (SOI) field effect transistor (402). The output of the dynamic input circuit (300) is low during the precharge mode. The output of the dynamic input circuit (300) corresponds to the input during the evaluate mode. The output of the dynamic input circuit (300) is used to gate the predischarging device.
Inventors:
DAVIES ANDREW DOUGLAS
STORINO SALVATORE N
TRAN JEFF V
WILLIAMS ROBERT RUSSELL
STORINO SALVATORE N
TRAN JEFF V
WILLIAMS ROBERT RUSSELL
Application Number:
PCT/US1999/019535
Publication Date:
November 09, 2000
Filing Date:
August 27, 1999
Export Citation:
Assignee:
IBM (US)
International Classes:
H01L21/8238; H01L27/08; H01L27/092; H01L29/786; H03K19/003; H03K19/094; H03K19/096; H03K19/20; (IPC1-7): H03K19/20
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