DIRECT DIGITAL FREQUENCY SYNTHESIS ENABLING SPUR ELIMINATION

Title:

DIRECT DIGITAL FREQUENCY SYNTHESIS ENABLING SPUR ELIMINATION

Document Type and Number:

WIPO Patent Application WO2000055973

Kind Code:

A3

Abstract:

The present invention, generally speaking, provides improved methods of generating clean, precisely-modulated waveforms, at least partly using digital techniques. In accordance with one aspect of the invention, a "difference engine" is provided that produces a digital signal representing the frequency error between a numeric frequency and an analog frequency. The frequency error may be digitally integrated to produce a digital signal representing the phase error. The difference engine may be incorporated into a PLL, where the analog frequency is that of an output signal of a VCO of the PLL. Direct modulation of the PLL output signal may be performed numerically. By further providing an auxiliary modulation path and performing calibration between the direction modulation path and the auxiliary modulation path, modulation characteristics may be separated from loop bandwidth constraints. In particular, the loop bandwidth of the PLL may be made so low as to reduce spurs (usually associated with DDS techniques) to an arbitrarily low level. A loop filter of the PLL may be realized in digital form. Using a digital loop filter would ordinarily require use of a high-resolution DAC. Various techniques are described for reducing the resolution requirements of the DAC.

Inventors:

SANDER BRIAN (US)
SANDER WENDELL (US)

Application Number:

PCT/US2000/006757

Publication Date:

December 28, 2000

Filing Date:

March 16, 2000

Export Citation:

Click for automatic bibliography generation Help

Assignee:

TROPIAN INC (US)
SANDER BRIAN (US)
SANDER WENDELL (US)

International Classes:

H03B28/00; H03C3/09; H03L7/08; H03L7/085; H03L7/18; H03L7/089; (IPC1-7): H03B21/00; H03L7/16

Foreign References:

US5554987A	1996-09-10
US5038120A	1991-08-06
US5604690A	1997-02-18

Other References:

PATENT ABSTRACTS OF JAPAN
PATENT ABSTRACTS OF JAPAN

Download PDF:

View/Download PDF PDF Help

Previous Patent: METHODS AND APPARATUS FOR BIPOLAR ELIMINATION IN SILICON-ON-INSULATOR (SOI) DOMINO CIRCUITS

Next Patent: BLOCK INTERLEAVE DEVICE, BLOCK DEINTERLEAVE DEVICE, BLOCK INTERLEAVE METHOD, AND BLOCK DEINTERLEAVE ...