Title:
METHODS FOR IMPROVED PLANARIZATION POST CMP PROCESSING
Document Type and Number:
WIPO Patent Application WO2002056343
Kind Code:
A3
Abstract:
The present invention provides a method for improving the planarization of a top layer deposited over a patterned layer on a semiconductor wafer. The patterned layer may include both small and large features. Openings, grooves, or trenches are etched partially or completely through certain larger target features in the patterned layer in an effort to mimic the topography of areas where the patterned layer includes smaller features. Subsequent deposition of the top layer may result in a more consistent or regular topography across the surface of the top layer. Accordingly, high areas on the top layer that contact a polishing pad of a CMP system will tend to be removed at a similar rate since the pressure exerted by each of the high areas will be similar.
Inventors:
HANSON ERIC IAN
Application Number:
PCT/US2002/000460
Publication Date:
April 17, 2003
Filing Date:
January 08, 2002
Export Citation:
Assignee:
HONEYWELL INT INC (US)
International Classes:
H01L21/302; H01L21/3105; H01L21/321; H01L21/461; H01L; (IPC1-7): H01L21/302; H01L21/461
Foreign References:
| US6051496A | 2000-04-18 | |||
| US6020249A | 2000-02-01 | |||
| US5928960A | 1999-07-27 | |||
| US5328553A | 1994-07-12 | |||
| US5139608A | 1992-08-18 |
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