Title:
MIXER CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2022/269860
Kind Code:
A1
Abstract:
A mixer circuit according to the present invention comprises: a power distributor (1) that distributes an LO signal at an equal amplitude and an equal phase; delay circuits (2-1 to 2-N); unit mixers (3-1 to 3-N); transmission lines (4-1 to 4-N); and a power synthesizer (6) that synthesizes, at an equal amplitude and equal phase, RF signals output from the unit mixers (3-1 to 3-N). When a phase delay amount, in relation to an IF signal, for each of the transmission lines (4-1 to 4-N) is denoted by ΔθIF, the phase delay amount of the LO signal due to the kth (k being an integer of 1 to N) delay circuit (2-k) counted from an IF port (41) side is set to θ1 - kΔθIF or to θ1 + kΔθIF.
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Inventors:
HAMADA HIROSHI (JP)
JO TERUO (JP)
JO TERUO (JP)
Application Number:
PCT/JP2021/023952
Publication Date:
December 29, 2022
Filing Date:
June 24, 2021
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H03D7/12
Domestic Patent References:
| WO2017216839A1 | 2017-12-21 |
Foreign References:
| JP2014116697A | 2014-06-26 | |||
| JPS61240705A | 1986-10-27 |
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
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