Title:
MULTI-BIT MEMORY DEVICE WITH NANOWIRE STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2022/262652
Kind Code:
A1
Abstract:
An approach for utilizing an IC (integrated circuit) that is capable of storing multi-bit in storage is disclosed. The approach leverages the use of multiple nanowires structures as channels (102), (105), (107) in a gate of a transistor. The use of multiple nanowires as channels (102), (105), (107) allows for different V t (i.e., voltage of device) to be dependent on the thickness of the fe (ferroelectric) layer (103), (104), (106) that surrounds each of the nanowire channels (102), (105), (107). Memory window is about 2d (thickness of a fe layer (103), (104), (106)). Setting voltage is also proportional to the fe layer (103), (104), (106) thickness. The V t of the device is the superposition of the various fe layers (103), (104), (106). For example, if there are three channels (102), (105), (107) with three different fe layer (103), (104), (106) (of varying thickness), then four memory states can be achieved. More states can be achieved based on the number of channels (102), (105), (107) in the device.
Inventors:
YU LAN (US)
YEUNG CHUN WING (US)
HUANG HUAI (US)
CHAO ROBIN (US)
YEUNG CHUN WING (US)
HUANG HUAI (US)
CHAO ROBIN (US)
Application Number:
PCT/CN2022/098106
Publication Date:
December 22, 2022
Filing Date:
June 10, 2022
Export Citation:
Assignee:
IBM (US)
IBM CHINA CO LTD (CN)
IBM CHINA CO LTD (CN)
International Classes:
H01L29/78; H01L21/335; H01L29/423
Foreign References:
| US20200303208A1 | 2020-09-24 | |||
| US20070176218A1 | 2007-08-02 | |||
| US20160181259A1 | 2016-06-23 | |||
| CN110707152A | 2020-01-17 | |||
| CN110416315A | 2019-11-05 |
Attorney, Agent or Firm:
ZHONGZI LAW OFFICE (CN)
Download PDF:
Previous Patent: 1S1R-TYPE MEMORY INTEGRATED STRUCTURE AND PREPARATION METHOD THEREFOR
Next Patent: GAS-LIQUID SEPARATOR AND AIR CONDITIONING DEVICE
Next Patent: GAS-LIQUID SEPARATOR AND AIR CONDITIONING DEVICE