Title:
MULTIPLIER-ACCUMULATOR
Document Type and Number:
WIPO Patent Application WO/2020/026947
Kind Code:
A1
Abstract:
Provided is a multiplier-accumulator with which it is possible, even in a precharge system that detects the magnitude of a current flowing in an output line, to sufficiently suppress a sneak current. A plurality of memory cells 17 in which a synaptic connection load is stored are arrayed in the form of a matrix in a synaptic computation unit. An output line MAL is connected to the memory cells 17 in each column, and input lines DL1, DL2, etc., are connected to the memory cells 17 in each row. The memory cells 17 are such that the output line MAL is precharged and is discharged as each of the memory cells 17 drains a cell current that corresponds to the synaptic connection load, and the potential drops. The memory cells 17 are configured from a memory element 21 in which a memory transistor MT, a drain-side transistor DT, and a source-side transistor ST are connected in series, the memory cells 17 being connected between the input lines DL1, DL2, etc., and the output line MAL. The memory transistor MT stores a synaptic connection load with a charge amount of a charge-storage layer 24.
Inventors:
YANAGISAWA KAZUMASA (JP)
HAYASHI TOMOICHI (JP)
NODA SATOSHI (JP)
TANIGUCHI YASUHIRO (JP)
OKUYAMA KOSUKE (JP)
HAYASHI TOMOICHI (JP)
NODA SATOSHI (JP)
TANIGUCHI YASUHIRO (JP)
OKUYAMA KOSUKE (JP)
Application Number:
PCT/JP2019/029299
Publication Date:
February 06, 2020
Filing Date:
July 25, 2019
Export Citation:
Assignee:
FLOADIA CORP (JP)
International Classes:
G06G7/60
Domestic Patent References:
| WO2016178392A1 | 2016-11-10 |
Foreign References:
| US20170228345A1 | 2017-08-10 |
Attorney, Agent or Firm:
DORAIT IP LAW FIRM (JP)
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