Background

Carbon nanotubes (CNTs) have become the most studied structures in the field of nanotechnology due to their remarkable electrical, thermal, and mechanical properties. In general, a carbon nanotube can be visualized as a sheet of graph paper with a hexagonal grid rolled up into a tube and seamlessly joined. Each line on the graph paper represents a carbon-carbon bond, and each intersection point represents a carbon atom. In general, CNTs are elongate tubular bodies which are typically only a few atoms in circumference. The CNTs are hollow and have a linear fullerene structure. Such elongated fullerenes having diameters as small as 0.4 nanometers (nm) and lengths of several micrometers to tens of millimeters have been recognized. Both single-walled carbon nanotubes (SWCNTs) and multi-walled carbon nanotubes (MWCNTs) have been recognized.

CNTs have been proposed for a number of applications because they possess a very desirable and unique combination of physical properties relating to, for example, strength to weight ratio. For instance, CNTs are being considered for a large number of applications, including without limitation field-emitter tips for displays, transistors, interconnect and memory elements in integrated circuits, scan tips for atomic force microscopy, and sensor elements for chemical and biological sensing. CNTs are either conductors (metallic) or semiconductors, depending on their diameter and the spiral alignment of the hexagonal rings of graphite along the tube axis. They also have very high tensile strengths. CNTs have demonstrated excellent thermal and electrical conductivity. For example, CNTs conduct heat and electricity better than copper or gold and have 100 times the tensile strength of steel, with only one-sixth of the weight of steel.

Various techniques for producing CNTs have been developed. The early processes used for CNT production were laser ablation and an arc discharge approach. More recently, chemical vapor deposition (CVD) is becoming widely used for growing CNTs. In this approach, a feedstock, such as CO or a hydrocarbon or alcohol, is heated to a temperature in the range from about 600 ⁰ C to about 1000° C with a transition metal catalyst to grow CNTs. Even more recently, plasma enhanced CVD (PECVD) has been proposed for use in producing CNTs. Using PECVD may permit CNTs to be grown at lower temperatures. Thus, in several production processes, such as CVD and PECVD, CNTs can be grown from a catalyst on a substrate surface, such as a substrate (e.g., silicon or quartz) that is suitable for fabrication of electronic devices, sensors, field emitters and other applications. For instance, using such techniques as CVD and PECVD, CNTs can be grown on a substrate (e.g., part of a wafer) of a material commonly used in known semiconductor fabrication processes. In general, the catalyst includes nanoparticles from which nanotubes grow during the growth process. Typically, one nanotube grows from each nanoparticle.

CNT growth using transition-metal catalyst nanoparticles in a CVD system has become a standard technique for growing single-wall and multi-wall CNTs for substrate-deposited applications. Various catalyst systems have been developed for CVD growth, including iron/molybdenum/alumina films, iron nanoparticles formed with ferritin, nickel/alumina films, cobalt-based catalyst films, and self-assembled arrays of nanoparticle catalysts formed using diblock copolymers.

CNTs exhibit one-dimensional ("1 D") electrical transport properties along their length. Semiconducting CNTs have been used to make field-effect transistors (FETs) with promising electrical characteristics. In typical FET implementations, the CNT is used as the channel of the FET. Electrical conduction through the CNT is controlled by a gate electrode that control electrical conduction through the CNT. The source and drain of the FET are typically provided by metal layers connected to the CNT. The CNTs are typically added into the device by either direct growth on the substrate or by

In all cases, the source and drain electrodes may be placed before or after CNT growth or dispersion. For either growth or dispersion, electrical contact is a random event that occurs whenever a semiconducting CNT connects the source and drain electrodes. It is possible to maximize the probability of having a single CNT connect the source and drain electrodes by adjusting the CNT density in suspension. However, this is not a manufacturable process. That is, the yield will be low because CNTs will not always grow or land such that they connect the source and drain electrodes. It is also possible to move as-deposited CNTs onto existing metal source and drain electrodes using some sort of micromanipulation, such as an AFM tip. This again is not a manufacturable process because manipulation of individual CNTs is too slow. One way to force alignment between the CNT and the source and drain electrodes is to pattern the catalyst layer from which the CNTs grow, grow the CNTs, then deposit the source, drain, and gate metals aligned to the original catalyst layer. Any CNTs that grow from the catalyst layer to the region where the source and drain electrodes are located would form an FET. Such a random process may be made less random by aligning the growing CNTs using an external electric field, or using an electric field provided by surface charge. However, applying an electric field either externally or by surface charge can be difficult and is often impractical. For instance, electric fields applied during growth of the nanotubes can ionize the precursor gases. For an external electric field applied using electrodes surrounding the growth chamber, the nanotubes will grow in only one direction, which severely limits options for orienting devices on the wafer. For electric- fields applied using electrodes on the wafer, the electrodes must be electrically contacted while in the growth chamber. Thus, a need exists for a manufacturable process for forming CNT-based FETs. Further, a need exists for such a process for forming CNT-based FETs that does not require that the direction of growth of the nanotubes be controlled (e.g., via an electric field). Further still, a need exists for such a process for forming CNT-based FETs having improved predictability in the performance of the resulting FETs.

Summary Embodiments of the invention provide nanostructure-based transistors, and methods for making such nanostructure- based transistors. More particularly, systems and methods are provided comprising a catalyst region; nanostructures extending from the catalyst region; a first electrode aligned with the catalyst region and greater in extent than the catalyst region; and a second electrode. At least one of the nanostructures extending from the catalyst region electrically connects the first electrode and the second electrode. In certain embodiments, the first electrode covers the catalyst region, while in other embodiments the first electrode underlies the catalyst region.

The second electrode is curvilinear, and is disposed around the first electrode. As used herein, annular is not limited to a circular annulus or any other shape of annulus. Also, as used herein, the term around is used broadly and is intended to encompass both partially around and fully surrounding. For instance, when referring to the second electrode as being around the first electrode, this is not intended to require that the second electrode fully surround the first electrode except where accompanying language specifies otherwise. Such second electrode may only be partially around the first electrode, unless accompanying language specifies that the second electrode fully surrounds the first electrode. As described further herein, in certain embodiments the second electrode fully surrounds the first electrode, while in other embodiments one or more gaps are provided in the second electrode such that it partially surrounds the first electrode.

^!; %tøle Wbόtfrtariotube's areiked1n'thB ^!! e1<emplary embodiments disclosed herein, the concepts provided herein are not limited in application to nanotubes. The electrodes may be electrically connected by other nanostructures that can be grown from a catalyst region, particularly nanostructures having high aspect ratios. Examples of such nanostructures are nanofibers, nanoribbons, nanothreads, nanowires, nanorods, nanobelts, nanosheets, and nanorings. The first electrode aligned with the catalyst region and the annular second electrode around the first electrode simply defines the alignment of the first and second electrodes with the nanostructures that extend from the catalyst region, irrespective of the directions in which the nanostructures grow from the catalyst region. Consequently, embodiments of the invention do not require that the direction of growth of the nanostructures be controlled, e.g., via an electric field. Further, embodiments of the invention provide greater consistency in the length of the nanostructures between the first and second electrodes and, hence, improved predictability in performance. Further, in certain embodiments, the annular second electrode is substantially equidistant to the first electrode. For instance, in certain embodiments, the annular second electrode is circular and concentric with the first electrode. Having such equidistant electrodes will produce a nanotube channel of equal length which is important for predictable performance. Embodiments described herein enable such predictability to be achieved without requiring actual alignment of the nanotubes. According to another embodiment, an apparatus comprises a catalyst region, nanostructures extending from the catalyst region, a first electrode aligned with the catalyst region and greater in extent than the catalyst region and an annular second electrode around the first electrode. At least one of the nanostructures electrically connects the first electrode and the second electrode. Certain implementations additionally comprise a third electrode between the first and second electrodes. Thus, the first electrode and the second electrodes may each be one of the source electrode and the drain electrode, and the third electrode may be the gate electrode of a field-effect transistor (FET).

There are advantages to making the catalyst region much smaller than the first electrode aligned with the catalyst region. Thus, according to another embodiment, an apparatus comprises a catalyst region, nanostructures extending from the catalyst region and a first electrode aligned with the catalyst region. The first electrode and the catalyst region have extents having a ratio equal to or greater than 1 :1. In certain implementations, the ratio of the extents of the first electrode and the catalyst region is at least 10:1. As used herein, the term "extent" refers to the dimensions of the first electrode and the catalyst region in a plane parallel to the major surface of the substrate on which the first electrode and catalyst region are located in the general direction in which current flows between the first and second electrodes.

In another aspect, the invention provides a radial field effect transistor comprising a catalyst region, nanostructures extending radially from the catalyst region, a first electrode a second electrode, and a gate electrode. The first electrode is greater in extent than the catalyst region and is in electrical contact with at least one of the nanostructures adjacent one end of the nanostructure adjacent the catalyst region. The second electrode is disposed about the first electrode and is in electrical contact with the at least one of the nanostructures adjacent the end of the nanostructure remote from the catalyst region. The gate electrode is located between the first electrode and the second electrode.

In a final aspect, the invention provides a method, comprising providing a substrate, forming a catalyst region on the substrate, forming a first electrode and a curvilinear second electrode about the first electrode, and growing nanostructures extending from the catalyst region. The first electrode is aligned with the catalyst region and is greater in extent than the catalyst region. At least one of the nanostructures electrically connects the first electrode and the second electrode.

¹ 'irϊif Description of the Drawings

Figures 1 A-1 H show an exemplary fabrication process for forming a nanostructure-based radial FET according to one embodiment of the invention;

Figure 2 shows a cross-sectional view of a nanostructure-based radial FET made by the exemplary fabrication process shown in Figures 1 A-1 H along the section line 2-2 in Figure 1 H;

Figures 3A and 3B each show other examples of a nanostructure-based radial FET according to embodiments of the invention;

Figure 4A shows a cross-sectional view of another example of a nanostructure-based radial FET according to another embodiment of the invention; Figure 4B shows a cross-sectional view of an exemplary nanostructure-based radial FET in which the gate electrode is disposed under the nanostructures according to another embodiment of the invention;

Figure 4C shows a cross-sectional view of yet another example of a nanostructure-based radial ET according to another embodiment of the invention;

Figure 4D shows a cross-sectional view of yet another example of a nanostructure-based radial ET according to another embodiment of the invention;

Figure 5 shows a cross-sectional view of an example of a stacked nanostructure-based radial FET according to another embodiment of the invention;

Figure 6 shows an example of a nanostructure-based radial FET having a segmented electrode according to another embodiment of the invention; Figure 7 shows an example of a catalyst region and juxtaposed electrode of a nanostructure-based radial FET having a segmented electrode according to another embodiment of the invention; and

Figure 8 shows an example of a linear nanostructure-based FET.

Detailed Description Figures 1 A-I H show an exemplary fabrication process for forming a nanostructure-based radial FET according to one embodiment of the invention. As described below, this exemplary fabrication process uses a catalyst region from which nanotubes extend. After nanotube growth, source, gate and drain metal electrodes are defined in alignment with the catalyst region. This forms a self-aligning FET without the need of using an electric field for arranging the nanotubes.

In Figure 1 A, a catalyst region 102 is located on a substrate 101. Catalyst region 102 includes nanoparticles that, when exposed to a nanostructure growth process, e.g., CVD or PECVD, result in the growth of nanostructures. While the catalyst region 102 has a circular shape in the example of Figure 1A, embodiments of the invention are not so limited. Instead, catalyst region 102 may have any desired shape.

Examples of known nanoparticles that may be included in catalyst region 102 for growing nanotubes as exemplary nanostructures include iron/molybdenum/alumina, iron nanoparticles formed with ferritin, nickel/alumina, cobalt-based particles, and particles formed using diblock copolymers. In one exemplary implementation, catalyst region 102 is formed by depositing a thin film of catalyst material on substrate 101. The thin film is then patterned using standard lithographic techniques, such as photolithography or electron-beam lithography, to define the catalyst region 102 with a desired size and shape at a desired location on substrate 101. In an example, a catalyst material for growing CNTs is spun-on or otherwise deposited on substrate 101 and is photolithographically patterned to define catalyst region 102 having a size in

the 101 is typically part of a wafer of substrate material, such as silicon.

Figure 1B shows substrate 101 after it has been subject to a nanostructure growth process. In this illustrated example, nanotubes 103A-103L as exemplary nanostructures have grown from at least some of the nanoparticles in catalyst region 102. While 12 nanotubes are shown in this example for illustrative purposes, any number of nanotubes may be grown in various implementations. During the growth process, the nanotubes 103A-103L grow outward from catalyst region 102. While the nanotubes 103A-103L grow in somewhat random directions, the circular geometry of catalyst region

102 results in the grown nanotubes extending substantially radially from the catalyst region. Moreover, the fraction of the nanotubes within a given angular deviation (e.g., ± 10°) of the radial direction increases with increasing distance from the center of catalyst region 102. The growth of nanotubes may be limited to growth from the periphery of catalyst region 102 using the techniques described in co-pending and commonly assigned U.S. Patent Application serial no. 11/035,595, incorporated by reference.

As shown in Figure 1C, after growth of the nanotubes 103A-103L, a metal layer is deposited and is patterned using standard microlithographic techniques to define drain metal 10 and source metal 11. In the example shown in Figure 1 C, drain metal 10 includes a drain electrode 105, drain pad 104, and drain lead 120 and source metal 11 includes a source electrode 107 and a source pad 106 electrically connected to the source electrode 107.

Drain electrode 105 is juxtaposed with catalyst region 102 and is greater in extent than catalyst region 102. In the example shown, catalyst region 102 and drain electrode 105 are circular in shape and are concentric with one another. Drain electrode 105 is greater in extent than catalyst region 102 in the sense that it is larger in diameter than catalyst region 102 and therefore extends in the radial direction beyond the perimeter of the catalyst region. Further, in this example, drain electrode 105 directly contacts catalyst region 102 and covers catalyst region 102. In the example shown, drain lead 120 electrically connects drain electrode 105 to drain pad 104.

Source electrode 107 is annular and is disposed around drain electrode 105 concentric with drain electrode 105. Source electrode 107 directly contacts nanotubes 103A-103L that extend from catalyst region 102 adjacent the ends of the nanotubes remote from catalyst region 102. In the example shown, source electrode 107 is connected to source pad 106.

While electrode 105 is referred to in this example as the drain electrode and electrode 107 is referred to in this example as the source electrode, in other embodiments, electrode 105 is the source electrode and electrode 107 is the drain electrode. This holds true for all of the exemplary embodiments described herein, i.e., the electrodes designated as the source electrode and the drain electrode may be interchanged in each embodiment. A layer of dielectric material is deposited and optionally is patterned as shown in Figure 1 D to define a gate insulator

108.

As shown in Figure 1 E, a layer of gate metal is deposited, and is patterned to define gate metal 12. In the example shown, gate metal 12 includes a gate electrode 110, a gate pad 109 and a gate lead 121. Gate electrode 110 is located between the source electrode 105 and the drain electrode 107. In the example shown, gate electrode 110 is curvilinear. Specifically, in the example shown, gate electrode 110 is annular, is disposed around drain electrode 105 between drain electrode 105 and source electrode 107 and is concentric with drain electrode 105. Thus, gate electrode 110 is located on gate insulator 108 over nanotubes 103A-103L that extend between drain electrode 105 and source electrode 107. In the example shown, gate lead 121 electrically connects gate electrode 110 to gate pad 109.

The pads shown in Figures 1 A-1 F, and in other of the figures hereof, are for illustrative purposes only and need not be

of th'e'ge'δnletry Irioinf orln to the electrodes shown.

As shown in Figure 1 F, an etch is performed to remove any nanotube segments that interconnect drain metal 11 and source metal 12 outside the gate electrode 110. This ensures that the drain metal and the source metal are not electrically connected by nanotubes whose electrical properties are not controlled by gate electrode 110. The etch electrically isolates the drain metal from the source metal except for the electrical coupling provided by the FET channel implemented by the nanostructures located under gate electrode 110. For instance, in the example shown in Figure 1E, nanotube 103A originally curves such that a portion of it, shown as 103Ashort, electrically connects source pad 106 and drain lead 120. However, portion 103Ashort is not located under gate electrode 110. The etch removes portion 103Ashort of nanotube 103A to ensure that drain metal 11 and source metal 12 are electrically connected only by the channel of the FET, i.e., by the nanostructures located under gate electrode 110. This etch operation may be omitted if it is improbable that drain metal 11 and source metal 12 are electrically connected by nanostructures not located under gate electrode 110.

A blanket passivation layer is then deposited and is patterned to expose pads 104, 106, and 109. Figure 1 G shows the device after a blanket passivation layer 114 has been deposited and has been patterned to expose the pads 104, 106, and 109. The material of blanket passivation layer is typically SiO ₂ or SiON (silicon oxynitride), but other materials can be used. In certain embodiments, the passivation layer 114 may be used as a dielectric layer to insulate the FET from another layer of metallization (not shown) deposited on the passivation layer.

As noted above, two types of nanotubes exist: metallic and semiconducting. Typically, one third (1/3) of the nanotubes grown as described above with reference to Figure 1 B are metallic. Growth processes designed to maximize the fraction of semiconducting nanotubes grown rarely achieve more than about 90% semiconducting nanotubes. Thus, even when relatively few nanotubes are grown, such as depicted in the example shown Figure 1 B, there is high probability that at least one of the nanotubes will be metallic. A metallic nanotube provides a low-resistance electrical connection between drain electrode 105 and source electrode 107 and prevents the device from exhibiting the properties of a transistor. Progress in CNT growth may one day allow 100% semiconducting nanotubes to be grown. In the mean time, growth processes typically provide a mixture of metallic and semiconducting nanotubes. As shown in Figure 1 H, metallic nanotubes are removed. In this example, metallic nanotubes are "burned out" using, for example, the technique described in United States Patent Nos. 6,423,583 and 6,706,566. In this technique, an appropriate voltage is applied to gate electrode 120 to minimize the conductivity of the semiconducting nanotubes. Then a high current is passed between drain electrode 105 and source electrode 107. The current flows mainly through any metallic nanotubes that may be present. Heat generated by the current flow through the residual resistance of the metallic nanotubes burns out such nanotubes. In the example shown in Figure 1H, nanotubes 103C, 103F, and 103 J are metallic nanotubes and have been removed by the burn out process. The finished FET is shown at 100.

It is possible that burn-out of the metallic nanotubes will work better when it is performed before passivation layer 114 is deposited to cover the nanotubes. Therefore, in certain embodiments, the burn-out process is performed before the nanotubes are covered with passivation layer 114. In other embodiments, the burn-out process is performed after passivation layer 114 is deposited.

Figure 2 shows a cross-sectional view of an FET 100 made by the exemplary fabrication process shown in Figures 1A-1H. As shown, the FET 100 includes a catalyst region 102, nanotubes (of which nanotubes 103D and 103K are shown) that extend from catalyst region 102, drain electrode 105 that that is greater in extent than catalyst region 102 juxtaposed with catalyst region 102, and source electrode 107. The nanotubes, such as nanotubes 103K and 103D, that extend from

catJyst'TedW 10$ ^' pΨoWcrePp'araffei eleclffcifpaths that electrically connect source electrode 107 to drain electrode 105. Gate electrode 110 is located between drain electrode 105 and source electrode 107 on gate insulator 108 over the nanotubes, such as nanotubes 103K and 103D. Thus, the nanotubes, such as nanotubes 103K and 103D, collectively constitute the channel of the FET. In some implementations, the gate insulator 108 may extend over at least part of the source and drain electrodes.

This depends on the deposition technique used to deposit the dielectric material in which gate insulator 108 is defined. In the example shown in Figure 2, the gate insulator does not extend over the source and drain electrodes. The thickness of the gate insulator, as well as the thicknesses of others of the elements shown in Figure 2, are not shown to scale for ease of illustration. FET 100 shown in Figure 2 has properties of a MOSFET. That is, semiconducting nanotubes 103A-103L (minus the removed metallic nanotubes 103C, 103F, and 103 J) provide a channel through which current flows in a substantially radial direction between drain electrode 105 and the source electrode 107. The electrical conductivity of the channel depends on the gate-to-source voltage V _gs applied between source electrode 107 and gate electrode 110. A small change in the gate- to-source voltage may cause a large variation in the current flow. While lateral dimensions are not specified in Figure 2, in certain implementations they will all be in the range from about 0.1 to about 10 μm. Lateral dimensions are dimensions in the X-direction shown in the figure. The lateral dimensions are defined by the lithographic process (e.g., either photolithography or e-beam lithography) used in the patterning processes that define the catalyst region, source electrode, drain electrode, gate electrode, etc. The lateral dimensions include the diameter of the drain electrode, the length of the gate electrode (hereinafter referred to as "gate length"), the spacing between the drain electrode and gate electrode, the spacing between the gate electrode and the source electrode, and the length of the source electrode (denoted Ls in Figure 1 C). The gate length in this exemplary configuration corresponds to the dimension of gate electrode 110 in the radial direction, and is labeled "L _g " in Figure 1 E. In devices intended for high-speed operation, the gate length "L _g " is made as short as possible. The minimum gate length is determined by the lithographic technique employed. Dimensions in the Z-direction shown in Figure 2 refer to the thicknesses of the layers and are controlled by the deposition processes.

The width Ls of source electrode 107 can be as wide as a given application allows to minimize parasitic source resistance and help heat sink the device. The spacings between a) the source electrode and the gate electrode and b) the gate electrode and the drain electrode involve a trade-off between channel resistance and gate-to-source and gate-to-drain capacitances. Large gate-to-source and gate-to-drain capacitances lower the device's maximum operating frequency. Thus, the source-to-gate and gate-to-drain spacings will depend on the application. In general, devices that have high maximum current ratings will have smaller source-to-gate and gate-to-drain spacings and devices with high frequencies of operation will have larger source-to-gate and gate-to-drain spacings. The trade-off between maximum current rating and maximum frequency of operation may be made less severe by chemically doping the portions of the nanotubes not located under the gate, source, and drain electrodes to lower the electrical resistance of these portions of the nanotubes. This allows the source-to-gate and gate-to-drain spacings to be increased to obtain a high maximum operating frequency without unduly increasing the channel resistance and, hence, without reducing the maximum current rating.

While Figures 1A-1 H show an exemplary fabrication process and Figure 2 shows exemplary FET 100 made by the exemplary fabrication process, the concepts described herein are not limited to this exemplary fabrication process and the exemplary FET.

" ^" FofinitSncyin^όiilv^fratidiήOn the exemplary fabrication process shown in Figures 1A-1H, the dielectric material in which gate insulator 108 is defined is deposited after nanotubes 103A-103L have been grown, but before deposition of the layer of metal in which the drain metal and source metal are defined. In this case, the dielectric material is patterned to define gate insulator 108 and is additionally patterned to expose portions of the nanotubes for contact with drain electrode 105 and source electrode 107 when these electrodes are subsequently formed. The dielectric material can be patterned before or after the gate metal is deposited on the dielectric material and is patterned to define the gate electrode 110.

In another variation, the nanotubes are grown, dielectric material is deposited and is patterned to define gate insulator 108 and to expose the ends of the nanotubes for contact with the drain and source electrodes. A layer of metal is then deposited and patterned to define the drain metal 11 and the source metal 12 in which the drain electrode 105 and the source electrode 107 electrically contact opposite ends of the nanotubes. The layer of metal is additionally patterned to define the gate metal 12 including the gate electrode 110 over the nanotubes and separated from the nanotubes by gate insulator 108.

As another variation, no gate insulator is formed. Instead, gate electrode 110 directly contacts the nanotubes, forming a Schottky gate. This can simplify the fabrication process at the expense of increased gate leakage current and smaller allowable gate voltage swing.

Another possible trade-off is involved in the configuration of gate electrode 110. In the example of FET 100 shown in

Figures 1 H and 2, gate electrode 110 surrounds the drain electrode 105 so that part of gate electrode 110 overlaps drain lead 120. Drain lead 120 electrically connects drain electrode 105 to drain pad 104. The region where the gate electrode and drain lead overlap may be the source of the majority of gate-to-drain capacitance of FET 100, especially in embodiments in which gate insulator 108 comprises a very thin layer (e.g., ~5 nm thick) of high-k dielectric material

The gate electrode can be configured to eliminate overlap between it and the drain lead. Figure 3A shows an example of an FET 300 in accordance with another embodiment of the invention. FET 300 has a discontinuous gate electrode 306 that defines a gap 308 aligned with drain lead 320 and dimensioned such that gate electrode 306 does not overlap any portion of drain metal 30. However, gap 308 in gate electrode 306 increases the length of the path through which a gate charging current charges the end of gate electrode 306 remote from gate lead 321. The increased path length can reduce the maximum frequency response of FET 300.

FET 300 shown in Figure 3A is made as follows, for example. After growth of the nanotubes 103A-103L from catalyst region 102, a layer of metal is deposited and is patterned using a standard lithographic technique to define a source electrode 301 and a drain electrode 304 aligned with catalyst region 102 (not shown). Specifically, the metal layer is patterned to define drain metal 30 that includes drain electrode 304 that is greater in extent than catalyst region 102. In this example, catalyst region 102 and drain electrode 304 are circular in shape and drain electrode 304 extends radially beyond the periphery of catalyst region 102. Drain metal 30 also includes a drain pad 303 and a drain lead 320 that electrically connects drain pad 303 to drain electrode 304.

The metal layer is also patterned to define source metal 31 that includes a source electrode 301 and a source pad 302 electrically connected to source electrode 301.

A layer of dielectric material is then deposited and is patterned as described above to define gate insulator 108 (not shown). A layer of metal is then deposited and is patterned to define gate metal 32 that includes discontinuous gate electrode 306, a gate pad 307, and a gate lead 321 that electrically connects gate pad 307 to gate electrode 306.

FET 100 shown in Figure 1 H has a continuous gate electrode 110 through which approximately equal portions of the

The equal and opposite current flows through continuous gate electrode 110 substantially eliminate any magnetic coupling between gate electrode 110 and source electrode 107. In FET 300 shown in Figure 3A, the gate charging current flows in only one direction through a discontinuous annular gate electrode 306. The unidirectional flow of the gate charging current through discontinuous gate electrode 306 causes magnetic coupling between gate electrode 306 and source electrode 301.

The above-described magnetic coupling between gate and source and the above-described capacitative coupling between gate and drain may both be eliminated by configuring the gate metal so that gate electrode is discontinuous and the gate lead connects to the gate electrode at a point opposite the gap through which the drain lead passes through the gate electrode, as shown in Figure 3B. In this, source electrode 301 is divided into two portions 301 A and 301 B that define an opening 305. Thus, the source electrode 301 is discontinuous in this example. Portions 301 A and 301 B directly contact ' nanotubes 103A-103L grown from catalyst layer 102. Portions 301 A and 301 B are electrically interconnected by a metal trace 330 defined in the same metallization as the electrodes 301 A and 301 B. Portions 301 A and 301 B may alternatively be electrically interconnected in other ways. Additionally, gate metal 32 is patterned to define discontinuous gate electrode 306 having a gap 308 through which drain lead 320 passes, as described above, and additionally to define gate lead 321 that passes through gap 305 in source electrode 301 to gate pad 307.

A layer of dielectric material is then deposited and optionally is patterned to define gate insulator 108 that covers the drain electrode 304, source electrode 301 and nanotubes 103A-103L. A layer of metal is then deposited and patterned to define gate metal 32 that includes gate electrode 306 aligned with the source electrode and the drain electrode. Gate electrode 306 is located between drain electrode 304 and the portions 301A-301 B of source electrode 301. Gate electrode 306 is annular and is concentric with and disposed around drain electrode 304. Thus, gate electrode 306 is disposed on gate insulator 108 over nanotubes 103A-103L that electrically connect drain electrode 304 and the portions 301A-301 B of source electrode 301. As described above, gate insulator/gate metal deposition may alternatively be performed before source/drain metal deposition.

In the examples described above, the nanotubes are located between the source, drain, and gate electrodes and substrate 101. In other examples, one or more of the source, drain, and gate electrodes are additionally or alternatively located between the nanotubes and the substrate, such as in the exemplary cross-sectional views shown in Figures 4A-4D described below. For instance, in an embodiment, the drain electrode and the source electrode are located on the substrate, a catalyst region is deposited and nanotubes are grown extending from the catalyst region. The catalyst region may be located on the source electrode or on the drain electrode. This locates the drain electrode and the source electrode between the nanotubes and the substrate.

In an example, cavities are etched in substrate 101 with shapes similar to the electrodes and a layer of metal is deposited on substrate 101. The metal is patterned to define drain metal 10 and source metal 11 having shapes and relative positions similar to those shown in Figure 1 C. Catalyst material is then deposited and is patterned to define catalyst region 102 on drain electrode 105 such that drain electrode 105 is greater in extent than the catalyst region 102. A nanostructure growth process (e.g., CVD or PECVD) is then performed to grow nanostructures, such as nanotubes 103A- 103L, extending from the catalyst region 102. The nanostructures electrically contact drain electrode 105 adjacent their proximal ends, i.e., their ends closer to the catalyst region, and electrically contact source electrode adjacent their distal ends, i.e., their ends further from the catalyst region. Fabrication processes similar to those described above with reference to Figures 1 D-1 H are then performed to complete the fabrication of the FET. In such examples, the cavities

ϊή'e'iύbkfatFaέcdϊnffl'fidaϊe the drain metal 10 and source metal 11 and a planarizing process is performed before catalyst region 102 is formed. Drain metal 10 and source metal 12 located in such cavities will be regarded as being on the substrate.

Other examples have a first part of either or both the drain electrode and the source electrode underlying the nanotubes as just described and a second part of either or both the drain electrode and the source electrode, respectively, overlying the nanotubes as described above with reference to Figure 1 C. Some examples of these possible variations are described next with reference to Figures 4A-4D.

Figure 4A shows a cross-sectional view of an example of an FET 400 according to another embodiment of the invention in which the nanotubes are located between a top gate electrode and a bottom gate electrode. This structure maximizes the effectiveness with which the gate electrodes apply the electric field to the nanotubes. FET 400 includes substrate 101, catalyst region 102, nanotubes 103A-103L extending from catalyst region 102, drain electrode 105 aligned with and greater in extent than catalyst region 102, source electrode 107, a top gate insulator 108, and a top gate electrode 110. FET 400 also includes a bottom gate electrode 401 located on the opposite side of the nanotubes from top gate electrode 110. The embodiment of FET 400 shown in Figure 4A is fabricated as follows. Substrate 101 is etched to define a cavity.

A layer of metal is deposited on substrate 101 and is patterned to define bottom gate electrode 401 located in the cavity. Typically, bottom gate electrode 401 has a shape similar to that of gate electrode 110 shown in Figure 1 E. Typically, the surface of the substrate is then planarized. A layer of dielectric material is deposited and is patterned to define bottom gate insulator 402. The fabrication processes described above with reference to Figures 1A-1H are then performed. The masks used in the patterning processes described above with reference to Figures 1 A-1 H are aligned with bottom gate electrode 401 so that drain electrode 105, source electrode 107 and top gate electrode 110 are concentric with annular bottom gate electrode 401 and annular top gate electrode 110 is located above and parallel to bottom gate electrode 401.

The materials of bottom gate electrode 401 and bottom gate insulator 402 have to be compatible with the subsequent processing, including withstanding the temperature of the nanotube growth process, which is typically in the range from about 600 ⁰ C to about 1000 ⁰ C.

Any technology capable of making bottom gate electrode 401 can additionally be used to make an embodiment of FET 400 in which top gate electrode 110 is omitted, i.e., an embodiment with only bottom gate electrode 401. A bottom gate only configuration has lower capacitance between the gate and the source and drain. An example of such an FET is shown in Figure 4B described below. In FET 400 shown in Figure 4A nanotubes 103A-103L are located between top gate electrode 110 and bottom gate electrode 401. This arrangement provides greater coupling between the gate electrodes and the nanotubes than a single gate electrode. This increases the speed of the FET. Top gate electrode 110 and bottom gate electrode 401, and drain electrode 105 and source electrode 107 are shaped in any suitable manner, including the respective shapes shown in Figure 1 H or the respective shapes shown in Figures 3A and 3B. Additionally, the cross-sectional dimensions, i.e., the thicknesses and lengths of the elements, may differ from the examples shown in the figures. As noted above, the figures are not necessarily to scale for ease of illustration.

Figure 4B shows a cross-sectional view of a second embodiment of FET 400. This embodiment has only a bottom gate electrode 401. Catalyst region 102 is located on gate insulator 108, the nanotubes extend from catalyst region 102, drain electrode 105 is located on and is greater in extent than catalyst region 102 and source electrode 107 contacts the

nanlϊ'uies It'fbcyoniymBtέ ^' fi'Bm'€raffi 'eifeSfode 105. The drain, source, and gate electrodes have shapes and relative positions similar to those described above with reference to Figures 1 A-1 H, i.e., the gate electrode 110 is located between the drain electrode 105 and the source electrode 107 but is located between the nanotubes and the substrate in this embodiment. The embodiment of FET 400 shown in Figure 4B is fabricated as follows. The substrate is etched to define a cavity, a metal layer is deposited and is patterned to locate gate electrode 401 in the cavity. The surface of the substrate is then planarized. Gate insulator 108 is then deposited and optionally is patterned. The catalyst region 102 is formed on gate insulator 108, nanotubes are grown extending from catalyst region 102, and a layer of metal is deposited and patterned to define source electrode 107 and drain electrode 105. Figure 4C shows a cross-sectional view of a third embodiment of FET 400 in which the drain, source, and gate electrodes are all located between the nanotubes and the substrate. In this embodiment, drain electrode 105, source electrode 107, and bottom gate electrode 401 are all located in cavities in substrate 101. Catalyst region 102 is located on, and is smaller in extent than, drain electrode 105. The nanotubes extend over gate insulator 108 from catalyst region 102 to contact source electrode 107 at locations remote from drain electrode 105. The drain, source, and gate electrodes have shapes and relative positions similar to those described above with reference to Figures 1 A-1 H, i.e., the gate electrode 110 is located between the drain electrode 105 and the source electrode 107. However, drain electrode 105, source electrode 107 and gate electrode 110 are all located between the nanotubes and the substrate in this embodiment.

The embodiment of FET 400 shown in Figure 4C is fabricated as follows. The substrate is etched to define cavities for the drain, source and gate electrodes. A metal layer is deposited and is patterned to locate drain electrode 105, source electrode 107 and gate electrode 401 in respective ones of the cavities. The surface of the substrate is then planarized. A layer of dielectric material is deposited to provide gate insulator 108 and is patterned to expose drain electrode 105 and source electrode 107. Catalyst region 102 is then formed on drain electrode 105 as described above and nanotubes are grown extending from the catalyst region into contact with source electrode 107.

Figure 4D shows a cross-sectional view of a fourth embodiment of FET 400 in which drain, source, and gate electrodes are located on both sides of the nanotubes. In this embodiment, a bottom drain electrode 105,, a bottom source electrode 107,, and a bottom gate electrode 401 are located in cavities in substrate 101. A bottom gate insulator 108, covers bottom gate electrode 401 but leaves bottom drain electrode 105, and bottom source electrode 107, exposed. The nanotubes extend from catalyst region 102 located on bottom drain electrode 1051 towards bottom source electrode 107,. A top gate insulator 108 ₂ covers the nanotubes but leaves bottom drain electrode 105, and bottom source electrode 107, exposed. A top drain electrode 105 ₂ is located over catalyst region 102 in contact with the catalyst region, the nanotubes and the bottom drain electrode. A top source electrode 107 ₂ is located over bottom source electrode 107, in contact with the nanotubes and the bottom source electrode. A top gate electrode 110 is located on top gate insulator 108 ₂ .

The embodiment of FET 400 shown in Figure 4D is fabricated as follows. The substrate is etched to define cavities for the drain, source and gate electrodes. A metal layer is deposited and is patterned to locate bottom drain electrode 105,, bottom source electrode 107, and bottom gate electrode 401 in respective ones of the cavities. The surface of the substrate is then planarized. A layer of dielectric material is deposited to provide gate insulator 108 and is patterned to expose bottom drain electrode 105, and bottom source electrode 107,. Catalyst region 102 is then formed on bottom drain electrode 105, as described above and nanotubes are grown extending from the catalyst region into contact with bottom source electrode 107,. A second layer of metal is deposited and is patterned to define top drain electrode 105 ₂ , top source

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As described above, gate electrode 110 and gate insulator 108 may be located between the nanotubes and substrate 101. Such implementations are made by depositing a metal layer on substrate 101 and patterning the metal layer to define gate metal 12. In the examples described above, the substrate is etched to define a cavity before the metal layer is deposited and is patterned. This locates the gate electrode 110 in the cavity and allows the surface of the substrate to be planarized. Gate insulator 108 is then deposited over the gate electrode.

Typically, connections between the electrodes and their respective pads are made by respective leads located in cavities defined in the substrate, with electrical connections to the remaining electrodes being made by respective leads located on the surface of the substrate. In embodiments in which leads and electrodes are located in cavities formed in the substrate, the surface of the substrate is planarized after such leads and electrodes have been formed. Planarization is a standard procedure in semiconductor process technology.

Certain FET embodiments in accordance with the invention have a stacked configuration in which one nanostructure- based transistor is stacked on top of another. A stacked configuration increases the maximum current rating of the FET without increasing the substrate area occupied by the FET. In an exemplary stacked configuration, the top gate electrode of a lower transistor element acts as the bottom gate electrode of an upper transistor element. Stacked configurations in which the stack comprises more than two transistor elements are also possible.

Figure 5 shows an example of a stacked configuration FET 500 according to an embodiment of the invention. In the example shown in Figure 5, FET 500 is composed of a stack of three transistor elements 501, 502, and 503. Other examples have more or fewer transistor elements than the example shown. FET 500 is fabricated as follows. First transistor element 501 is fabricated as described above with reference to

Figure 4A Thus, first transistor element 501 is located on substrate 101 and includes catalyst region 102, nanotubes 103A- 103L (of which only nanotubes 103 J and 103D are shown) extending from the catalyst region, drain electrode 105 aligned with and having an extent greater than catalyst region 102, source electrode 107, top gate insulator 108, top gate electrode 110, bottom gate insulator 402, and a bottom gate electrode 401. Drain electrode 105 typically has the same shape as drain electrode 105 shown in Figure 1 H. Source electrode 107 typically has the same shape as source electrode 107 shown in Figure 1 H, source electrode 301 shown in Figure 3A or source electrode 301 shown in Figure 3B. Top gate electrode 110 and bottom gate electrode 401 typically have the same shape as gate electrode 110 shown in Figure 1 H, gate electrode 306 shown in Figure 3A or gate electrode 306 shown in Figure 3B. Transistor element 501 is planarized by a layer 504 of dielectric material such as SiO2. Transistor element 502 and transistor element 503 are then fabricated in order on top of transistor element 501. Each transistor element 502 and 503 is fabricated in a manner similar to that described above. In one exemplary embodiment, transistor element 502 is fabricated as follows. A layer of dielectric material is deposited over transistor element 501 and is patterned to define bottom gate insulator 402 ₂ over gate electrode 110 of first transistor element 501. The layer of dielectric material is additionally patterned to expose drain electrode 105 and source electrode 107 of first transistor element 501. Catalyst region 102 ₂ is then formed on drain electrode 105. A nanostructure growth process, such as CVD or PECVD, is then performed to grow nanostructures (nanotubes in this example) extending from catalyst region 102 ₂ . Exemplary nanotubes 103 ₂ are shown in Figure 5. A layer of metal is deposited and is patterned to define a drain electrode 105 ₂ and a source electrode 107 ₂ aligned with catalyst region 102 ₂ . This alignment additionally aligns drain electrode 105 ₂ and source electrode 107 ₂ with the underlying drain electrode 105 and source electrode 107, respectively, of first transistor

elentenl"5C$ .' Drlifi 0 ^' S ₂ ¹ rs' defϊrieifito cover and extend beyond the catalyst region 102 ₂ . Drain electrode 105 ₂ typically has the same shape as drain electrode 105.

Annular source electrode 107 ₂ surrounds the drain electrode 105 ₂ of second transistor element 502. Source electrode

107 ₂ typically has the same shape as the source electrode 107 of first transistor element 501. In the example shown, drain electrode 105 ₂ directly contacts catalyst region 102 ₂ and the nanotubes 103 ₂ extending from catalyst region 102 ₂ , and additionally contacts the drain electrode 105 of first transistor element 501. Similarly, source electrode 107 ₂ directly contacts the nanotubes 103 ₂ extending from catalyst region 102 ₂ adjacent their ends remote from catalyst region 102. Source electrode 107 ₂ additionally contacts the source electrode 107 of first transistor element 501. Consequently, the drain electrode 105 of first transistor element 501 and the drain electrode 105 ₂ of second transistor element 502 are electrically connected, and the source electrode 107 of first transistor element 501 and the source electrode 107 ₂ of second transistor element 502 are electrically connected.

Gate insulator 402 ₂ is formed over gate electrode 110 of first transistor element 501 before the nanotubes 103 ₂ of second transistor element 502 are grown and is located between nanotubes 103 ₂ and first transistor element 501. Gate insulator 402 ₂ insulates nanotubes 1032 from the bottom gate electrode of second transistor element 502, i.e., gate electrode 110. After nanotubes 103 ₂ have been grown, a layer of dielectric material is deposited and is patterned to define a gate insulator 1082. The layer of dielectric material is additionally patterned to expose the drain electrode 105 ₂ and the source electrode 107 ₂ of transistor element 502.

A layer of metal is then deposited and is patterned to define a top gate electrode 110 ₂ of second transistor element 502. Top gate electrode 110 ₂ is aligned with the drain electrode 105 ₂ and the source electrode 107 ₂ of second transistor element 502. Consequently, the gate electrode 110 of first transistor element 501 and the gate electrode 110 ₂ of second transistor element 502 provide the gate electrodes for the channel (nanotubes 103 ₂ ) of second transistor element 502. Gate electrode 110 ₂ has the same shape as the gate electrode 110 of first transistor element 501.

A layer 504 of dielectric material such as SiO ₂ is then deposited and a planarization process is performed to planarize second transistor element 502. Third transistor element 503 is formed on top of second transistor element 502. In an exemplary embodiment, transistor element 503 is fabricated as follows. A layer of dielectric material is deposited on transistor element 502 and is patterned to define a gate insulator 402 ₃ over the gate electrode 11O ₂ of second transistor element 502. The layer of dielectric material is additionally patterned to expose the drain electrode 105 ₂ and the source electrode 107 ₂ of second transistor element 502. Catalyst region 102 ₃ is then formed on drain electrode 1052. A nanostructure growth process, such as CVD or PECVD, is then performed to grow nanostructures (nanotubes in this example) extending from catalyst region 102 ₃ . Exemplary nanotubes 103 ₃ are shown in Figure 5. A layer of metal is deposited and is patterned to define a drain electrode 105 ₃ and a source electrode 107 ₃ aligned with catalyst region 102 ₃ . This additionally aligns drain electrode 105 ₃ and source electrode 107 ₃ with the underlying drain electrode 105 ₂ and source electrode 107 ₂ of second transistor element 502. Drain electrode 105 ₃ is defined to cover and extend beyond catalyst region 102 ₃ . Drain electrode 105 ₃ typically has the same shape as the drain electrode 105 of first transistor element 501.

Annular source electrode 107 ₃ surrounds the drain electrode 105 ₃ of third transistor element 503. Source electrode

107 ₃ typically has the same shape as the source electrode of first transistor element 501. In the example shown, the drain electrode 105 ₃ directly contacts catalyst region 102 ₃ and the nanotubes 103 ₃ extending from catalyst region 102 ₃ , and additionally contacts the drain electrode 105 ₂ of second transistor element 502. Similarly, source electrode 107 ₃ directly

coniiysnfiy ⁱ riaMuHbέ ¹ "ib3 ₃ ' ^' e)AintJinιf'frDMϊatalyst region 102 ₃ and additionally contacts the source electrode 107 ₂ of second transistor element 502. Consequently, the drain electrode 105 ₂ of second transistor element 502 and the drain electrode 105 ₃ of third transistor element 503 are electrically connected, and the source electrode 107 ₂ of second transistor element 502 and the source electrode 107 ₃ of third transistor element 503 are electrically connected. Gate insulator 402 ₃ is formed over gate electrode 1102 of second transistor element 502 before the nanotubes 103 ₃ of third transistor element 503 are grown and is located between nanotubes 103 ₃ and second transistor element 502. Gate insulator 402 ₃ insulates nanotubes 103 ₃ from the bottom gate electrode of third transistor element 503, i.e., gate electrode 11 O ₂ . After nanotubes 103 ₃ have been grown, a layer of dielectric material is deposited and is patterned to define a gate insulator 108 ₃ . A layer of metal is then deposited and is patterned to define a gate electrode 11O ₃ of third transistor element 503.

Gate electrode 110 ₃ is aligned with the drain electrode 105 ₃ and the source electrode 107 ₃ of third transistor element 503. Typically, the gate electrode 110 ₃ of third transistor element 503 has the same shape as the gate electrode 110 of first transistor element 501. The gate electrode 11O ₂ of second transistor element 502 and the gate electrode 11O ₃ of third transistor element 503 respectively provide the bottom gate electrode and the top gate electrode for the channel (nanotubes 103 ₃ ) of third transistor element 503. Gate electrodes 401, 110, 11 O ₂ and 11O ₃ are electrically connected in parallel (not shown) and to a gate pad (not shown) of FET 500.

The operations described above with reference to Figures 1 F-1 H may additionally be performed in the course of fabricating each transistor element 501-503. For example, an etch as described above with reference to Figure 1 F may be performed on each transistor element to ensure that the drain metal and source metal of each transistor element are electrically isolated except for the coupling provided by the nanostructures controlled by the respective gate electrodes. However, an operation similar to that described above with reference to Figure 1 H in which metallic nanotubes are burned out is typically performed only once after all the transistor elements 501 -503 have been fabricated.

An embodiment of FET 500 having N transistor elements has a maximum current rating about N times that of each transistor element but has gate-to-drain (C _gd ) and gate-to-source (C _gs ) capacitances much less than N times the gate-to- drain (C _gd ) and gate-to-source (C _gs ) capacitances, respectively, of the transistor element since these capacitances are mostly due to fringing fields. In embodiments in which C _gs and C _gd are dominated by the fringing capacitance, _Cgs and C _gd of the FET increase sub-linearly with N.

As mentioned above, one practical consideration in fabricating a transistor having nanostructures as its channel is that current growth techniques result in a fraction (e.g., 1/3) of the nanostructures being metallic, rather than semiconducting. If not removed, metallic nanostructures short out the transistor action of the device. One exemplary technique for removing the metallic nanotubes is described above with reference to Figure 1 H.

Another way to addressing the issue of metallic nanostructures is to segment source electrode 107. Figure 6 shows an example of a nanostructure-based radial FET 600 in accordance with another embodiment of the invention in which source electrode 607 is segmented. In the example shown, source electrode 607 is composed of segments 107A-107 J disposed around drain electrode 105. While 10 segments are shown in this example, other embodiments have other numbers of segments. The segmented configuration of FET 600 allows testing to be performed to identify the metallic nanotubes and allows such metallic nanotubes to be isolated. With the metallic nanotubes isolated, the FET becomes a set of parallel FETs whose respective sources can be connected together to make a FET without metallic nanotube(s).

Figure 6 shows an example in which, after segments of source electrode 607 contacting metallic nanotubes have

etched away so that they no longer contact the metallic nanotubes, for example, metallic nanotube 60. The segments identified as contacting a metallic nanotube and that contact more than one nanotube (for example, segment 107B contacting nanotubes 61 and 62, and segment 107H contacting nanotubes 63 and 64) may also be etched to divide them into subsegments each of which contacts no more than one nanotube. The possibility of the etching process unintentionally disconnecting a nanotube is reduced by making the spacings between the subsegments of source electrode 607 small. On the other hand, having more than one nanotube connected to a single segment of source electrode 607 still helps with isolating the metallic nanotubes present in the device, but gives rise to the possibility of also having to disconnect the semiconducting nanotubes of a set of nanotubes that contact a segment of source electrode 607 that additionally contacts a metallic nanotube. There are several ways to identify the source electrode segments 107A-107 J that contact a metallic nanostructure.

During test, simple wafer probing of individual transistor structures is employed with each source electrode segment 107A-107 J being contacted by a respective probe. A bias is applied to gate electrode 110 and the electrical resistance between each source electrode segment and drain electrode 105 is measured. A source electrode segment whose measured electrical resistance is below a threshold is identified as a source electrode segment that contacts a metallic nanostructure. Once the source electrode segments that contact metallic nanotubes have been identified, the probes contacting remaining source electrode segments are connected in parallel to allow the characteristics of the resulting transistor to be measured. Wire bonding may be used to make permanent connections between the source electrode segments 107A-107J not identified as contacting metallic nanostructures to a common source pad corresponding to source pad 106 shown in Figure 1H. Another way to make a more automated connection to segmented source electrode 607 is to provide two pads for each source electrode segment. One of the pads is connected to the source electrode segment and the other of the pads is connected to a common source pad corresponding to source pad 106 shown in Figure 1H. The two pads are electrically connected by a metal fuse. The fuse between the pads connected each source electrode segment identified as contacting a metallic nanotube is electrically blown to disconnect the source electrode segment from the common source pad. An electric current passed between the pads heats the fuse to the point of destruction, and creates an open circuit. The process leaves only those source electrode segments that do not contact metallic nanotubes connected to the common source pad. Alternatively, anti-fuses, each typically comprising a Metal-lnsulator-Metal capacitor, can be used instead of the fuses just described. The anti-fuse between the pads connected to each source electrode segment identified as not contacting a metallic nanostructure is blown to create an electrical connection between the pads. Then, only those source electrode segments identified as not contacting a metallic nanostructure are connected to the common source pad.

Finally, CMOS (or other semiconductor transistor technology) transistors may be used instead of the above-described fuses or anti-fuses. The CMOS transistor connected to between each source electrode segment identified as contacting a metallic nanostructure and the common source pad is turned off to disconnect the source electrode segment from the common source pad. The material of substrate 101 in the above-described fabrication processes is typically SiO2, but is not limited to this material. Optimum metals for the source, drain, and gate electrodes include palladium for the source electrode and the drain electrode. Palladium has been shown to make a very good ohmic contact with semiconducting CNTs with diameters in the range of 1.5 to 2 nm. Such CNTs are by nature slightly p-type. Typical metals for the gate electrode are aluminum or titanium, but again any metal is possible, and the choice would depend on the processing compatibility and desired

threl ^' hdld vδltagl.-'btSllclπc ^!r n1atSftafs de'po ^' sϊfeϊϋ by atomic layer deposition (ALD) make good gate insulators in CNT-based FETs. The gate insulator and the metal top gate electrode described above with reference to Figures 1 D and 1 E may be replaced by a back gate provided by a heavily doped region of the silicon substrate and a gate insulator provided by a layer of thermal oxide formed by oxidizing the substrate. Alternatively, the FET may incorporate both a semiconductor back gate and a metal top gate.

As will be described in more detail below, it is advantageous for the catalyst region to much smaller than the drain electrode on or under which the catalyst region is located. For instance, it is advantageous for catalyst region 102 to be much smaller than drain electrode 105 in the example of FET 100 shown in Figures 1 H and 2 described above. Figure 7 shows catalyst region 102 and drain electrode 105 overlying catalyst region 102. Alternatively, drain electrode 105 may underlie catalyst region 102, as described above. In the example shown in Figure 7, catalyst region 102 has a radius RC, and drain electrode 105 has a radius RE. Referring briefly to Figure 1 B, nanotubes 103A-103L grow from catalyst region 102 in random directions. As a result of their random growth directions, the nanotubes can cross to form nanotube crossing. See, e.g., nanotubes 103E and 103F shown in Figure 1B. As will be described in more detail below, nanotube crossings that occur under the gate electrode impair the conduction characteristics of the FET by reducing the ability of the gate electrode to control the conductivity of the nanotube separated from the gate electrode by another nanotube crossing between the nanotube and the gate electrode. This is not an issue in embodiments, such as that described above with reference to Figure 4A, in which the CNTs are located between top and bottom gate electrodes.

In accordance with an aspect of the invention, the ill effects of nanotube crossings occurring under the gate electrode are mitigated by making most nanotube crossings occur in contact with drain electrode 105. This is done by making the drain electrode 105 greater in extent than the catalyst region 102. As the extent of the drain electrode 105 increases beyond that of catalyst region 102, the fraction of the nanotube crossings that occur in contact with the drain electrode 105 increases, and the fraction of nanotube crossings that occur under the gate electrode decreases. In the sense in which it is used in this disclosure, the term "extent" refers to the dimensions of an object in a plane parallel to the major surface of the substrate 101 in the general direction in which current flows between the drain electrode and the source electrode. In the example shown in Figure 7, in which catalyst region 102 and drain electrode 105 are both circular in a plane parallel to the surface of substrate 101, the extent of catalyst region 102 and the extent of drain electrode 105 are represented simply by the radius R _c of catalyst region 102 and the radius R _E of drain electrode 105. In addition, the smaller the extent of the catalyst region, the more likely any nanotube crossings will occur close to the catalyst region and, hence, the more likely they will occur in contact with the drain electrode. In an exemplary embodiment, R _E /R _C « 10. That is, the ratio of the radius R _E of drain electrode 105 and the radius R _c of the catalyst region 102 is approximately 10:1. In other words, the radius R _E is approximately 10 times the radius R _c in this embodiment. Since, at the periphery of drain electrode 105, the angle α between the longitudinal axis of each nanotube 103 and the direction of a radius 151 extending from the center of catalyst region 102 is no more than ~Rc/R _E radians, increasing the ratio R ₆ ZR ₀ decreases the angle between the nanotubes and the radius and, hence, likelihood of the nanotube crossings. Reducing the range of angular deviations between the nanotubes and the radial direction additionally makes the lengths of nanotubes between the source electrode and drain electrode more uniform. While a drain electrode 105 having an extent larger by any amount than that of catalyst region 102 is beneficial, in certain embodiments, a ratio of the extents of the drain electrode 105 and the catalyst region 102 equal to or greater than 1 :1 is beneficial. In embodiments in which the ratio of the extents is 1 :1, the drain electrode can still cover a significant fraction of the nanotube crossings

becausfe''δuih'1rMib ^; i! y4E'nalfbtdbe'" ^' B'rδisfh ^: |s occur within the catalyst region. The fraction depends on the extent of the catalyst region. In other applications, it is beneficial for the extents of the drain electrode and the catalyst region to have a larger ratio, for example, at least 2:1 or at least 10:1 (as described above). Any ratio of the extents of the drain electrode and the catalyst region of greater than or equal to 1 :1 is intended to be encompassed hereby. Figure 8 shows a nanostructure-based linear FET 800. The radial FETs in accordance with embodiments of the invention described above with Figures 1 H-6 will be briefly compared with the linear FET 800 shown in Figure 8 to show the advantages provided by the radial FET configuration.

In the linear FET shown in Figure 8, a catalyst region 808 is a narrow strip of catalyst material located on a substrate 801. Catalyst region 808 extends in the x-direction shown in Figure 8. Nanotubes 80 extend in random directions from catalyst region 808. A drain electrode 802 covers catalyst region 808. In this embodiment, the extent of catalyst region 808 and the extent of drain electrode 802 are represented by the dimensions of the catalyst region and the drain electrode, respectively, in the general direction of current flow from drain electrode 802, i.e., in the y-direction. Source electrodes 803 and 804 are disposed parallel to drain electrode 802 and are offset from the drain electrode in the plus y-direction and the - y-direction, respectively. Source electrodes 803 and 804 are electrically connected to one another by an external connection (not shown).

Gate electrode 805 is located over nanotubes 80 between drain electrode 802 and source electrode 803. Gate electrode 806 is located over nanotubes 80 between drain electrode 802 and source electrode 804 and is electrically connected to gate electrode 805. Gate electrodes 805 and 806 are insulated from the underlying nanotubes 80 by respective gate insulators (not shown), in a manner similar to described above with reference to the radial FETs. In an alternative embodiment, source electrode 804 and gate electrode 806 are omitted.

In the linear FET shown, the probability that any pair of nearby nanotubes 80 extending from catalyst region 808 will cross before reaching source electrode 805 or source electrode 806 is nearly 50%. Additionally, some of the nanotubes extend from catalyst region 808 towards source electrodes 805 and 806 at relatively small angles. In the description of Figure 8, angles are measured relative to the x-direction. As noted above, nanotube crossings can impair the characteristics of FET 800, especially when they occur under the gate electrode 805 or gate electrode 806, since the gate electrode has less ability to control the conductivity of a nanotube separated from the gate electrode by another nanotube crossing between the nanotube and the gate electrode. Moreover, the lengths of the paths between drain electrode 802 and source electrodes 803 and 804 provided by those of nanotubes 80 that extend from catalyst region 808 at small angles is much greater than the length of the paths provided by those of nanotubes 80 that extend from the catalyst region at large angles. The longer paths have higher resistance. Additionally, the longer paths have a longer path length under gate electrodes 805 or 806. The higher resistance and the longer path length under the gate electrode collectively reduce transconductance and operational speed.

Radial FETs according to embodiments of the invention have a central drain electrode and catalyst region, and a curvilinear source electrode and a curvilinear gate electrode disposed around the drain electrode. Compared with the linear FET shown in Figure 8, the radial FETs have superior characteristics as a result of a significantly reduced number nanotube crossings occurring under the gate electrode, a greater uniformity in the lengths of the paths provided by the nanotubes from the source electrode to the drain electrode, and a greater uniformity in the lengths of the paths provided by the nanotubes under the gate electrode. Accordingly, the radial FETs have more consistent and predictable performance than the linear FET.

" ^'" TrW c!)rtlisyn^Md ^" |)Vedi§ab'iiity ^:!l of''M6 ^|! performance of the linear FET described above with reference to Figure 8 can be improved by increasing the ratio of the extents of the drain electrode 802 and the catalyst region 801 in a manner similar to that described above with reference to Figure 7, and by additionally decreasing the separation between the source electrodes 803 and 804 and the drain electrode 802. Increasing the ratio of the extents of the drain electrode 802 and the catalyst region 801 can eliminate from the gate region the nanotubes that extend from the catalyst region at a small angles. Such nanotubes result in most of the nanotube crossings and cause the distribution of path lengths to have a long tail. However, even when the measures described above are implemented, the linear FET has a significantly larger number of nanotube crossings under the gate electrode, and a larger variability in the path lengths between source and drain and in the path lengths under the gate electrode than radial FETs according to embodiments of the invention. In the radial FETs according to embodiments of the invention described above with reference to Figures 1 H-6, the nominal direction in which the nanotubes extend from the catalyst region towards the source electrode is the radial direction, i.e., along a radius extending from the center of the catalyst region towards the source electrode. The maximum deviation from the nominal radial direction of the direction of any nanotube at the periphery of the drain electrode is ~Rc/R _E , the ratio of the radius of the catalyst region to the radius of the drain electrode. The maximum deviation of the nanotube direction from the nominal direction is much smaller in radial FETs according to embodiments of the invention than in the linear FET shown in Figure 8. The smaller maximum deviation reduces both the chance of nanotube crossings under the gate electrode and reduces the variability in path lengths provided by the nanotubes.

This disclosure describes the invention in detail using illustrative embodiments. However, the invention defined by the appended claims is not limited to the embodiments described.