Title:
NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
Document Type and Number:
WIPO Patent Application WO/2017/086399
Kind Code:
A1
Abstract:
According to the present invention, electrode layers 24, 26 are connected to a bismuth ferrite layer 22 by being arranged so as to sandwich the bismuth ferrite layer 22 from a direction that is perpendicular to the c-axis of a bismuth ferrite crystal that constitutes the bismuth ferrite layer 22. An electric field in a direction that is perpendicular to the c-axis of the bismuth ferrite crystal is applied to the bismuth ferrite layer 22 by applying a voltage between the electrode layers 24, 26. Consequently, the present invention is able to provide a nonvolatile memory having low power consumption, to which data is able to be written.
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Inventors:
TOKUNAGA MASASHI (JP)
KAWACHI SHIROU (JP)
ITO TOSHIMITSU (JP)
KUROE HARUHIKO (JP)
KAWACHI SHIROU (JP)
ITO TOSHIMITSU (JP)
KUROE HARUHIKO (JP)
Application Number:
PCT/JP2016/084156
Publication Date:
May 26, 2017
Filing Date:
November 17, 2016
Export Citation:
Assignee:
UNIV TOKYO (JP)
NAT INST ADVANCED IND SCIENCE & TECH (JP)
SOPHIA SCHOOL CORP (JP)
NAT INST ADVANCED IND SCIENCE & TECH (JP)
SOPHIA SCHOOL CORP (JP)
International Classes:
H01L27/105; G11C11/22; H01L45/00; H01L49/00
Domestic Patent References:
| WO2004107466A1 | 2004-12-09 | |||
| WO2006009218A1 | 2006-01-26 |
Foreign References:
| JP2013008884A | 2013-01-10 | |||
| JP2010007121A | 2010-01-14 | |||
| JP2007110068A | 2007-04-26 | |||
| JP2005011931A | 2005-01-13 | |||
| JP2015220445A | 2015-12-07 |
Attorney, Agent or Firm:
ITEC INTERNATIONAL PATENT FIRM (JP)
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