Field of the Invention

The present invention relates to an optoelectronic device and method of manufacture thereof.

Background

In optoelectronic devices there can be significant optical loss when a standard single mode fibre, with a typical mode size of 10.6pm at a wavelength of 1.55 pm, couples to a silicon waveguide which might have a mode size ranging from submicron to 3 pm (depending on the silicon-on-insulator, SOI, platform used) due to mode mismatching.

To minimise the coupling loss, 13pm x 13pm silicon waveguides have been used since the mode size matches that of the standard single mode fibre. Mode converters, or tapers, are used to adiabatically transition the mode from the 13pm x 13pm waveguide to a smaller silicon waveguide in the SOI platform. However, current solutions, such as double SOI mode converters, have complicated fabrication processes which result in high optical loss and a lower device yield.

There is a desire then, for a fabrication process to provide mode converters with a lower optical loss and with a higher device yield.

Summary

Accordingly, in a first aspect, embodiments of the present invention provide a method of manufacturing an optoelectronic device including a mode converter, the method having the steps of:

on a first silicon-on-insulator (SOI) wafer, manufacturing the optoelectronic device; and either:

on a second SOI wafer, manufacturing a mode converter, and bonding the mode converter to the first SOI wafer;

or

bonding a second SOI wafer to the first SOI wafer to form a combined wafer; and etching a mode converter into the combined wafer. Such a method results in simpler manufacturing process, and therefore to a higher manufacturing yield. Moreover, devices so fabricated have a lower optical loss.

Optional features of embodiments of the invention will now be set out. These are applicable singly or in any combination with any aspect of the invention.

Multiple mode converters may be manufactured on the second SOI wafer or the combined wafer.

In a second aspect, embodiments of the present invention provide a method of

manufacturing an optoelectronic device including a mode converter, the method having the steps of:

on a first SOI wafer, manufacturing the optoelectronic device;

on a second SOI wafer, manufacturing the mode converter; and

bonding the mode converter to the first SOI wafer.

Manufacturing the mode converter on the second SOI wafer may include the steps of: disposing a first photoresist over a portion of a device layer of the second SOI wafer; and

etching the exposed regions of the device layer to form the mode converter.

The mode converter may be formed as a tapered waveguide, which decreases in width along a direction parallel to the guiding direction of the waveguide.

Manufacturing the mode converter on the second SOI wafer may include a step of preparing the second SOI wafer for a micro-transfer printing process. Preparing the second SOI wafer for the micro-transfer printing process may include a step of: patterning a tether onto the mode converter; and removing an insulator layer between the mode converter and a silicon substrate of the second SOI wafer, thereby leaving the mode converter suspended via the tether.

The step of manufacturing the mode converter on the second SOI wafer may be performed before, or simultaneously with, the step of manufacturing the optoelectronic device on the first SOI wafer.

Bonding the mode converter to the first wafer may be performed via a micro-transfer printing process. The micro-transfer printing process may include a plasma treatment step and an annealing step, to bond the mode converter to a bonding region of the first wafer. Manufacturing the optoelectronic device may include the step of: manufacturing an input waveguide and/or an output waveguide on the first SOI wafer.

The optoelectronic device may be an electro-optic modulator, a laser, or a detector, and manufacturing the optoelectronic device may include the steps of: etching a device cavity into a device layer of the first SOI wafer; and growing an optically active region in the device cavity. Manufacturing the optoelectronic device may further comprise the step of: etching the grown optically active region in the device cavity to form an optically active waveguide. The optoelectronic device may be an electro-optic modulator or a detector, and manufacturing the optoelectronic device may further include: doping two or more regions of the optically active waveguide; and disposing an electrode in electrical contact with a respective doped region of the optically active waveguide. The optoelectronic device may be referred to as a photonic integrated circuit (PIC).

Manufacturing the optoelectronic device further includes a step, performed before bonding the second wafer to the first wafer, of: disposing a cover layer over the optoelectronic device, leaving one or more bonding regions, for bonding the first wafer to the second wafer, exposed.

The method may further include a step of manufacturing a further mode converter on the second SOI wafer or on another SOI wafer, and bonding said further mode converter to the first SOI wafer.

In a third aspect, embodiments of the present invention provide a method of manufacturing an optoelectronic device including a mode converter, the method having the steps of:

on a first SOI wafer, manufacturing an optoelectronic device;

bonding a second SOI wafer to the first SOI wafer to form a combined wafer; and etching a mode converter into the combined wafer.

Manufacturing the optoelectronic device may include a step of: manufacturing an input waveguide and/or an output waveguide on the first SOI wafer.

The optoelectronic device may be: an electro-optic modulator, a laser, a detector, an arrayed waveguide grating, an echelle grating, a Mach-Zehnder interferometer, a ring resonator, or any combination thereof. The optoelectronic device may be an electro-optic modulator, a laser, or a detector, and manufacturing the optoelectronic device may include the steps of: etching a device cavity into a device layer of the first SOI wafer; and growing an optically active region in the device cavity. Manufacturing the optoelectronic device may further include the step of: etching the grown optically active region in the device cavity to form an optically active waveguide. The optoelectronic device may be an electro-optic modulator, or a detector, and manufacturing the optoelectronic device may include the steps of: doping two or more regions of the optically active waveguide; and disposing an electrode in electrical contact with a respective doped region of the optically active waveguide.

Manufacturing the optoelectronic device may include a step, performed before bonding the second wafer to the first wafer, of: disposing a cover layer over the optoelectronic device, leaving one or more bonding regions, for bonding the first wafer to the second wafer, exposed.

The method may include, prior to bonding the second SOI wafer to the first SOI wafer, a step of: etching a second cavity into a device layer of the second SOI wafer. Bonding the second SOI wafer to the first SOI wafer may include: inverting the second SOI wafer, and disposing it on an upper surface of the first SOI wafer.

In a further step, a silicon substrate of the second SOI wafer may be removed after the second SOI wafer is bonded to the first SOI wafer.

In a further step, a buried oxide layer of the second SOI wafer may be removed after the second SOI wafer is bonded to the first SOI wafer.

Bonding the second SOI wafer to the first SOI wafer may be performed via a wafer bonding process. The wafer bonding process may be a plasma assisted wafer bonding process. The wafer bonding process may include a step of annealing the first SOI wafer and the second SOI wafer. The anneal may be performed at a temperature of at least 250°C.

The method may include a step of etching multiple mode converters into the combined wafer.

In a fourth aspect, embodiments of the present invention provide an optoelectronic device including a mode converter manufactured according to the method of any of the preceding aspects. Further aspects of the present invention provide: a computer program comprising code which, when run on a computer, causes the computer to perform the method of the first, second, or third aspect; a computer readable medium storing a computer program comprising code which, when run on a computer, causes the computer to perform the method of the first, second, or third aspect; and a computer system programmed to perform the method of the first, second, or third aspect.

Brief Description of the Drawings

Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which:

Figure 1A and 1 B show a top-down and cross-sectional view of an optoelectronic device including a mode converter;

Figure 2A and 2B show a top-down and cross-sectional view of a variant optoelectronic device including a mode converter;

Figure 3A and 3B show a top-down and cross-sectional view of a variant optoelectronic device including a mode converter;

Figure 4A and 4B show a top-down and cross-sectional view of a variant optoelectronic device including a mode converter;

Figures 5(i) - 5(xvi)(B) show various manufacturing stages of the optoelectronic device including a mode converter of Figure 1 A and 1 B;

Figures 6(i) - 6(viii)(B) show various manufacturing stages to prepare an optoelectronic device for integration with a mode converter;

Figures 7(i) - 7(v)(B) show various manufacturing stages to prepare a mode converter for integration with an optoelectronic device; and

Figures 8(i)(A) - 8(ii)(B) show an integration process of a mode converter with an optoelectronic device. Detailed Description and Further Optional Features

Aspects and embodiments of the present invention will now be discussed with reference to the accompanying figures. Further aspects and embodiments will be apparent to those skilled in the art.

Figure 1A and 1 B show a top-down and cross-sectional view of a photonic device 100 respectively. Broadly, the device 100 includes a 13 pm to 3 pm tapered waveguide 101 a which functions as a mode converter for light entering the device (on the left-hand most edge). The light is converted from the optical mode of an input fibre (not shown) to a 3 pm optical mode supported by 3 pm waveguide 102b. The light then enters an optoelectronic device 103, which includes a 3 pm waveguide.

The process is then reversed, and as the light exits the optoelectronic device 103 is it coupled into a 3 pm tapered waveguide 102b which is coupled to a 3 pm to 13 pm tapered waveguide 101 b. The light is converted from a 3 pm mode to a 13 pm mode, and is then transmitted onwards via an output fibre (not shown).

Figure 1 B is a cross-section view taken along the line A-A’ of Figure 1 A. This view shows in more detail the structure of the photonic device 100. As can be seen, the tapered waveguides 101 a and 10b sit atop a 3 pm silicon slab 104. This slab is bordered on a lower side (distal to the tapered waveguides) by a buried oxide layer 106. In this example, the buried oxide layer is formed of silicon dioxide, and functions as a lower cladding layer for the 3 pm silicon waveguides 102a and 102b. On an opposing side of the buried oxide layer 106 to the waveguides is a silicon substrate 107.

As discussed previously, the optoelectronic device 103 may be: an electro-absorption modulator; a laser; a detector; an arrayed waveguide grating; an echelle grating; a Mach- Zehnder interferometer, a ring resonator, or any combination thereof. The optoelectronic device in this example is an electro-absorption modulator. In examples where the component is a laser, there may be only an output fibre, i.e. only waveguides 102b and 101 b which connect to an output fibre. Similarly, in examples where the component is a detector, there may be only an input fibre, i.e. only waveguides 101 a and 102a.

Figure 2A and 2B show a top-down and cross-sectional view of a variant photonic device 200. Where the device 200 shares features with the device shown in Figure 1 A and 1 B, like features are indicated by like reference numerals. In contrast to the device 100 shown in Figure 1 A and 1 B, the light passing through device 200 undergoes a two-stage mode conversion process.

As before, light enters the device 200 into the left hand side of 13pm to 3 pm tapered waveguide 101 a. The light undergoes a mode conversion, and is provided into a 3pm to 1 pm tapered waveguide 201 a. In a second mode conversion step, the light is then converted to a mode supported by 1 pm waveguide 202a which is optically connected to a 1 pm based optoelectronic device 204. As before, the sequence is then reversed, with the light being coupled from the optoelectronic device 204 to 1 pm waveguide 202b, before being coupled first to the 1 pm to 3 pm tapered waveguide 201 b and subsequently to the 3 pm to 13 pm tapered waveguide 101 b.

Figure 3A and 3B show a top-down and cross-sectional view of a variant photonic device 300. Where the device 300 shares features with the device shown in Figure 1 A and 1 B, like features are indicated by like reference numerals. In contrast to the device 100 shown in Figure 1A and 1 B, the light passing through device 300 undergoes a two-stage mode conversion process.

As before, light enters the device 300 into the left hand side of 13pm to 3pm tapered waveguide 101 a. The light undergoes a mode conversion, and is provided into a 3pm to 800 nm tapered waveguide 301 a. In a second mode conversion step, the light is then converted to a mode supported by 800 nm waveguide 302a, which is optically connected to a 800 nm based optoelectronic device 304. As before, the sequence is then reversed, with the light being coupled from the optoelectronic device 304 to 800 nm waveguide 302b, before being coupled first to the 800 nm to 3 pm tapered waveguide 201 b and subsequently to the 3 pm to 13 pm tapered waveguide 101 b.

Figure 4A and 4B show a top-down and cross-sectional view of a variant photonic device 400. Where the device 400 shares features with the device shown in Figure 1 A and 1 B, like features are indicated by like reference numerals. In contrast to the device 400 shown in Figure 1A and 1 B, the light passing through device 300 undergoes a three-stage mode conversion process.

As before, light enters the device 400 into the left hand side of 13pm to 3 pm tapered waveguide 101 a. The light undergoes a mode conversion, and is provided into a 3 pm to 1 .5 pm tapered waveguide 402a. In a second mode conversion step, the light is provided to 1 .5 pm to 220 nm tapered waveguide 403a. In a third mode conversion step the light is then converted to a mode supported by 220 nm waveguide 204a, which is optically connected to a 220 nm based optoelectronic device 405. As before, the sequence is then reversed, with the light being coupled from the optoelectronic device 405 to 220 nm waveguide 404b, before being coupled to the 220 nm to 1 .5 pm tapered waveguide 403b. Next, the light is coupled to 1 .5 pm to 3 pm tapered waveguide 402b, before being provided to 3 pm to 13 pm tapered waveguide 101 b.

Figures 5(i) - 5(xvi)(B) show various manufacturing stages of the photonic device of Figure 1 A and 1 B. In a first step, shown in Figure 5(i), a silicon-on-insulator wafer is provided. The wafer comprises a silicon device layer 501 , a buried oxide layer 106, and a silicon substrate 107. In this example, the silicon device layer is around 3 pm tall, as measured from an uppermost surface of the buried oxide layer to an uppermost surface of the silicon device layer.

Next, in a step shown in Figure 5(ii), a hard mask 502 is provided over a portion of the upper surface of the device layer, and a cavity 503 is etched through the silicon device layer 501 and also through the buried oxide layer 106. This etch may be performed in two-steps, a first using the buried oxide layer as an etch stop, and a second using the silicon substrate as an etch stop. After this etch, a silicon cladding layer 505 is epitaxially grown from the silicon substrate, and a silicon germanium stack 504 is epitaxially grown on top of the silicon cladding layer. This is shown in Figure 5(iii) The silicon cladding layer has a composition such that it functions as a bottom cladding layer for a waveguide subsequently formed from the silicon germanium stack 504. For example, the silicon cladding layer may have a composition such that the refractive index of the cladding layer is lower than that of the silicon germanium stack.

After the silicon germanium stack 504 is provided, it is planarized relative to surrounding surfaces via a chemical-mechanical planarian process. The result of this is shown in Figure 5(iv). Next, a portion of the silicon device layer and the silicon germanium stack are etched to provide silicon rib waveguides 102a and 102b either end of, and which couple into, a silicon germanium rib waveguide 506. This is shown in Figures 5(v)(A) and 5(v)(B), where Figure 5(v)(A) is a cross-section taken along the line A-A’ in Figure 5(B). As can be seen in Figure 5(v)(A) and 5(v)(B), a silicon germanium slab 507 is retained. The etch is performed so that a space, x, from a sidewall of the cavity to the beginning of a taper region to the 3 pm waveguide is provided. This allows the bonding steps, discussed in detail below, to be more flexible in alignment. Portions of the upper surface of the device are covered by silicon dioxide covering 508.

Subsequently, in a step the results of which are shown in Figures 5(vi)(A) and 5(vi)(B), doped regions are added to the silicon germanium rib waveguide 506 and slab 507. Figure 5(vi)(A) is a cross-section taken along the line A-A’ of Figure 5(vi)(B). As can be seen, sidewalls of the silicon germanium rib waveguide 506 are doped. On one side, a p-type species of dopant is used to provide a p doped region 509 which extends down the sidewall. On the other side, an n-type species of dopant is used to provide an n doped region 511 which extends down the sidewall. A vertical p-i-n junction is thereby provided. A portion of the slab is heavily doped with a p-type species of dopant, to provide a p+ doped region 510 in the slab. Similarly, a portion of the slab is heavily doped with an n-type species of dopant, to provide an n+ doped region 513 in the slab.

After this, a silicon dioxide layer 515 is disposed over the exposed surfaces of the device and vias are opened above the p+ doped region 510 and n+ doped regions 512. A metallization step is performed, so as to provide a p-electrode 513 and n-electrode 514 which electrically connect to the p+ doped region 510 and n+ doped region 512 respectively. The result of this is shown in Figures 5(vii)(A) and (B), Figure 5(vii)(A) being a cross-section of Figure 5(vii)(B) along the line A-A’. Next, in a step shown in Figure 5(viii)(A) and 5(viii)(B), a silicon nitride layer 516 is disposed to cover the electrodes 513 and 514. As is shown in Figure 5(viii)(B) bonding areas 517 located at lateral ends of the device are left exposed. As before, Figure 5(viii)(A) is a cross-section view along the line A-A’ in Figure 5(viii)(B).

Next, in a step shown in Figure 5(ix)(A), a second SOI wafer is prepared. The second SOI wafer in this example has a 10 pm device layer 518 located above a buried oxide layer 519, which is supported by substrate 520. A cavity 521 is etched, the cavity corresponding in location and size to the cavity 503 etched previously. As before, Figure 5(ix)(A) is a cross- section along the line A-A’ shown in Figure 5(ix)(B).

Subsequently, the second SOI wafer is bonded to the bonding areas 517 of the first SOI wafer. The second SOI wafer is inverted, and the 10 pm device layer 518 is placed in contact with the bonding areas 517 of the first SOI wafer. A plasma assisted bonding process is used, with an annealing temperature of at least 300°C. The result is shown in Figure 5(x), where 10pm device layer 517 is bonded to the silicon device layer 501 of the first SOI wafer. The distance x, between the silicon nitride 516 and a sidewall of the 10 miti device layer 518 may be 1 mm or up to around 1 cm to facilitate bonding alignment.

After the wafer bonding step, the silicon substrate 520 is removed either by a chemical- mechanical planarization process or a dry etch. The result of this is shown in Figure 5(xi). Subsequently, in a step the result of which is shown in Figure 5(xii), the buried oxide layer 519 is removed either by a chemical-mechanical planarization process or a wet etch. This then allows a hard mask 522 to be disposed over a portion of the upper surface of the structure, for an etching step used to produce the 13 pm to 3 pm tapered waveguide. Figure 5(xiii) shows a cross-section through the line A-A’ discussed previously after the hard mask 522 has been provided.

The hard mask 522 is then patterned, and the 13 pm to 3 pm tapered waveguide is etched. This is shown in Figures 5(xiv)(A) and 5(xiv)(B), where 5(xiv)(A) is a cross-section along the line A-A’ in 5(xiv)(B). The hard mask is then removed, as well as the silicon nitride layer 516, after which a silicon dioxide top cladding layer 523 is deposited above the upper surface of at least the waveguides. This is shown in Figure 5(xv)(A), which is a cross-sectional view along the line A-A’ of Figure 5(xv)(B). Note that the top cladding is omitted in Figure 5(xv)(B) for clarity. Next, in a step shown in Figure (xvi)(A), the silicon dioxide top cladding layer 523 above the p-electrode 513 and the n-electrode 514 is removed to allow electrical contacts to be connected to the respective electrodes.

Figures 6(i) - 6(viii)(B) show various manufacturing stages to prepare an optoelectronic device for integration with a mode converter. They correspond to the steps shown in Figures 5(i) to 5(vii) discussed above. In a first step, shown in Figure 6(i), a silicon-on-insulator, SOI, wafer is provided. The SOI wafer comprises a silicon device layer 501 , which is above a buried oxide layer 106. The buried oxide layer is between the silicon device layer 501 and a silicon substrate 107.

Next, in a step shown in Figure 6(ii), a hard mask 502 is provided over a portion of the upper surface, and a cavity 503 is etched through the silicon device layer and also through the buried oxide layer. This etch may be performed in two-steps, a first using the buried oxide layer as an etch stop, and a second using the silicon substrate as an etch stop. After this etch, a silicon cladding layer 505 is grown from the silicon substrate, and a silicon germanium stack 504 is epitaxially grown on top of the silicon cladding layer. This is shown in Figure 6(iii). The silicon cladding layer has a composition such that it functions as a bottom cladding layer for a waveguide subsequently formed from the silicon germanium stack 504. For example, the silicon cladding layer may have a composition such that the refractive index of the cladding layer is lower than that of the silicon germanium stack.

After the silicon germanium stack 504 is provided, it is planarized relative to surrounding surfaces via a chemical-mechanical planarian process. The result of this is shown in Figure 6(iv). Next, a portion of the silicon device layer and the silicon germanium stack are etched to provide silicon rib waveguides 102a and 102b either end of, and which couple into, a silicon germanium rib waveguide 506. This is shown in Figures 6(v)(A) and 6(v)(B), where Figure 6(v)(A) is a cross-section taken along the line A-A’ in Figure 6(B). As can be seen in Figure 6(v)(A) and 6(v)(B), a silicon germanium slab 507 is retained.

The etch is performed so that a space, x, from a sidewall of the cavity to the beginning of a taper region to the 3 pm waveguide is provided. This allows the bonding steps, discussed in detail below, to be more flexible in alignment. Portions of the upper surface of the device are covered by silicon dioxide covering 508.

Subsequently, in a step the results of which are shown in Figures 6(vi)(A) and 6(vi)(B), doped regions are added to the silicon germanium rib waveguide 506 and slab 507. Figure 6(vi)(A) is a cross-section taken along the line A-A’ of Figure 6(vi)(B). As can be seen, sidewalls of the silicon germanium rib waveguide 506 are doped. On one side, a p-type species of dopant is used to provide a p doped region 509 which extends down the sidewall. On the other side, an n-type species of dopant is used to provide an n doped region 51 1 which extends down the sidewall. A vertical p-i-n junction is thereby provided. A portion of the slab is heavily doped with a p-type species of dopant, to provide a p+ doped region 510 in the slab. Similarly, a portion of the slab is heavily doped with an n-type species of dopant, to provide an n+ doped region 513 in the slab.

After this, a silicon dioxide layer 515 is disposed over the exposed surfaces of the device and vias are opened above the p+ doped region 510 and n+ doped regions 512. A metallization step is performed, so as to provide a p-electrode 513 and n-electrode 514 which electrically connect to the p+ doped region 510 and n+ doped region 512 respectively. The result of this is shown in Figures 6(vii)(A) and (B), Figure 6(vii)(A) being a cross-section of Figure 6(vii)(B) along the line A-A’. After the electrodes have been provided, bonding areas 517 at either end of the device are opened as is shown in Figure 6(viii)(B). The structure is then ready for integration with the mode converter fabricated with reference to Figures 7(i) -7(v)(B).

Figures 7(i) - 7(v)(B) show various manufacturing stages to prepare a mode converter for integration with an optoelectronic device. In a first step, shown in Figure 7(i) an SOI wafer is provided comprising: a 10 pm silicon device layer 701 , a buried oxide layer 702, and a silicon substrate 703. Next in a step shown in Figures 7 (i i) (A) , a cross-section view, and 7(ii)(B), a top-down view, a silicon dioxide hard mask 704 is provided and a photoresist 705 provided and patterned on top of the hard mask 704. The photoresist 705 has a triangular geometry, so as to define a waveguide tapering from a first width to a second width.

The etch is then performed, resulting in a structure shown in Figures 7(iii)(A) and 7(iii)(B), where Figure 7(iii)(A) is a cross-section view through the structure of Figure 7(iii)(B). A tapered waveguide 706 is shown, resulting from the etch. The photoresist has been removed. A further etch is performed, to remove the hard mask and also the exposed regions of the buried oxide layer 702, i.e. those portions of the buried oxide layer not sandwiched between the waveguide 706 and substrate 703. The result of this subsequent etch is shown in Figures 7(iv)(A) and 7(iv)(B), Figure 7(iv) being a cross-section view through the structure of 7(iv)(B).

Next, a photoresist tether 707 is disposed on the lateral sides and upper surface of the waveguide 706. This facilitates a further etch, which removes the remaining buried oxide layer, and leaves the waveguide 706 tethered to the silicon substrate 703 only be photoresist tether 707. The waveguide 706 can then be printed via a micro-transfer printing process, e.g. through attaching to an elastomer stamp.

Figures 8(i)(A) - 8(ii)(B) show an integration process of a mode converter with an optoelectronic device. The waveguide 706 is printed via the micro-transfer printing process to bonding area 517 of the structure shown in Figure 6(viii)(B). Subsequently, in a step shown in Figure 8(ii)(A) and Figure 8(ii)(B), a silicon dioxide top cladding layer 515 is disposed over the upper surface of the structure, and openings are formed in the cladding for p-electrode 513 and n-electrode 514.

The steps above, notably fabrication of a mode converter and bonding to a separate structure, can be repeated to provide a plurality of mode conversion steps such as that shown in Figures 2A - 4B. Alternatively, the adhesion of an inverted SOI wafer to the structure, as discussed with respect Figures 5(ix)(A) - 5(xii) can also be repeated so as to provide a plurality mode converters. Each mode converter after the first being bonded to the previously bonded mode converter. Further alternatively, a single slab or mode converter may be bonded to the structure, and then multiple etching steps can be performed to provide the plurality of mode converters.

While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when given this disclosure. Accordingly, the exemplary embodiments of the invention set forth above are considered to be illustrative and not limiting. Various changes to the described embodiments may be made without departing from the spirit and scope of the invention.

List of Features

100 Photonic device 507 Silicon germanium slab

101 13mhi to 3mGP tapered waveguide 508 Silicon dioxide covering

102 3pm waveguide 509 P doped sidewall

103 Optoelectronic device 510 P+ doped slab

104 3pm silicon slab 51 1 N doped sidewall

105 Silicon slab for 3pm waveguide 512 N+ doped slab

106 Buried oxide layer 513 P electrode

107 Silicon substrate 514 N electrode

200 Photonic device 515 Silicon dioxide layer

201 3pm to 1 pm tapered waveguide 516 Silicon nitride layer

202 1 pm waveguide 517 Bonding area

203 Silicon slab for 1 pm waveguide 518 10pm silicon on insulator layer

204 Optoelectronic device 519 Buried oxide layer

205 1 pm silicon slab 520 Silicon substrate

300 Photonic device 521 Cavity

301 3pm to 800nm tapered waveguide 522 Hard mask

302 800nm waveguide 523 Silicon dioxide cladding

303 Silicon slab for 800nm waveguide 701 10 pm silicon device layer

304 Optoelectronic device 702 Buried oxide layer

305 800nm silicon slab 703 Silicon substrate

400 Photonic device 704 Silicon dioxide hard mask

402 3pm to 1 5pm tapered waveguide 705 Photoresist

403 1 5pm-0.22pm tapered waveguide 706 Tapered waveguide

404 0.22pm tapered waveguide 707 Photoresist tether

405 Optoelectronic device

406 Silicon slab for 0.22pm tapered waveguide

407 0.22pm silicon slab

501 Silicon device layer

502 Hard mask

503 Cavity

504 Epitaxially grown silicon germanium

505 Epitaxially grown silicon cladding layer

506 Silicon germanium rib waveguide