Title:
OUTPUT DETERMINATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/167193
Kind Code:
A1
Abstract:
This output determination circuit (4) is created by a hard-wired scheme in which instructions are executed by means of hardware connections. The output determination circuit (4) decides an output signal (9) of a Field Programmable Gate Array (FPGA) operating according to logic information. The output determination circuit (4) is provided with a majority circuit (5). An output of each of a plurality of FPGAs performing the same operation is connected to the majority circuit (5). The majority circuit (5) performs a majority decision with respect to the outputs of the plurality of FPGAs to decide the output signal (9) from the outputs from the plurality of FPGAs. The majority circuit (5) is composed only of logical operation elements.
Inventors:
NOZAKI HIROHIDE (JP)
OGAWA YOSHIHIRO (JP)
OGAWA YOSHIHIRO (JP)
Application Number:
PCT/JP2018/007634
Publication Date:
September 06, 2019
Filing Date:
February 28, 2018
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H03K19/003; H03K19/177
Domestic Patent References:
| WO2015068207A1 | 2015-05-14 |
Foreign References:
| JP2010134678A | 2010-06-17 | |||
| JPH11251884A | 1999-09-17 | |||
| JPH05216702A | 1993-08-27 |
Attorney, Agent or Firm:
MIZOI INTERNATIONAL PATENT FIRM (JP)
Download PDF: