Title:
PHASE INTERPOLATION CIRCUIT, RECEPTION CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2022/168210
Kind Code:
A1
Abstract:
This phase interpolation circuit generates, on the basis of a first input clock signal and a second input clock signal having a first phase difference, an output clock signal having a phase in accordance with a phase interpolation code, and comprises: a first generation circuit which, in accordance with a phase interpolation code and on the basis of a first input clock signal, generates a first intermediate current; a second generation circuit which, in accordance with a phase interpolation code and on the basis of a second input clock signal, generates a second intermediate current; a combining circuit which combines the first intermediate current and the second intermediate current to generate an output clock signal; and a correction circuit which, on the basis of a correction current in accordance with a correction code that is set in accordance with at least a deviation amount of the first phase difference from a prescribed value, corrects amount of the first intermediate current and/or the second intermediate current.
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Inventors:
KANO HIDEKI (JP)
Application Number:
PCT/JP2021/003969
Publication Date:
August 11, 2022
Filing Date:
February 03, 2021
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H03L7/081
Domestic Patent References:
| WO2017154191A1 | 2017-09-14 |
Foreign References:
| US20160182216A1 | 2016-06-23 | |||
| JP2014146869A | 2014-08-14 | |||
| JP2008072234A | 2008-03-27 |
Attorney, Agent or Firm:
KOKUBUN, Takayoshi (JP)
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