PHASE-LOCKED LOOP - FUJITSU GENERAL LTD

Title:

PHASE-LOCKED LOOP

Document Type and Number:

WIPO Patent Application WO/2001/022593

Kind Code:

A1

Abstract:

For prompt restoration of a PLL being in inactive state due to an abnormal oscillation of a voltage-controlled oscillator, it is checked that a frequency divider (4) provides a comparison signal (fc). If no comparison signal (fc) is detected, a phase comparator (1) is forced to decrease its output level temporarily to decrease the oscillating frequency of the voltage-controlled oscillator (3). The method is suitable for generation of a wide range of sampling clocks to be used for the digital processing of analog video signals.

Inventors:

KIMURA TAKUSHI (JP)
NAKAJIMA MASAMICHI (JP)

Application Number:

PCT/JP2000/005629

Publication Date:

March 29, 2001

Filing Date:

August 23, 2000

Export Citation:

Click for automatic bibliography generation Help

Assignee:

FUJITSU GENERAL LTD (JP)
KIMURA TAKUSHI (JP)
NAKAJIMA MASAMICHI (JP)

International Classes:

H03L7/10; H03L7/095; H03L7/18; (IPC1-7): H03L7/083

Foreign References:

JPH10107627A	1998-04-24
JPH06338786A	1994-12-06

Other References: