Title:
TWO-STAGE MULLER C-ELEMENT
Document Type and Number:
WIPO Patent Application WO2001022591
Kind Code:
A9
Abstract:
A Muller C-element comprises two stages. The first stage consists of a NAND and a NOR gate, each driven by all of the inputs to the Muller C-element. In the second stage, the outputs of the two gates are used separately to switch on and off two output transistors, which drive the output of the Muller C-element. A keeper flip flop serves to retain the output value between changes. Because current from each gate is applied only to one output transistor, delay is reduced. Furthermore, an unneeded output transistor is switched off as soon as logically possible, often during the otherwise unused interval while the input values differ, which reduces both delay and crossover current. In a preferred embodiment, the NAND and NOR gates each comprise a set of series transistors and a set of parallel transistors. The parallel transistors in these gates work together to change the output value when all inputs are changing simultaneously, thereby allowing the use of parallel transistors having widths narrower than those normally employed in NAND and NOR gates. Use of smaller transistors renders the inputs easier to drive, improving the speed of the circuit.
Inventors:
FAIRBANKS SCOTT M (US)
Application Number:
PCT/US2000/026379
Publication Date:
November 14, 2002
Filing Date:
September 25, 2000
Export Citation:
Assignee:
SUN MICROSYSTEMS INC (US)
FAIRBANKS SCOTT M (US)
FAIRBANKS SCOTT M (US)
International Classes:
G06F9/38; H03K19/20; (IPC1-7): H03K19/177; G06F11/20; G11C5/00; G06F1/10; H03K19/08; H03K19/003
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