Title:
PIPELINE CIRCUIT, SEMICONDUCTOR DEVICE, AND PIPELINE CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2011/004532
Kind Code:
A1
Abstract:
Provided is a pipeline circuit capable of flexibly controlling clock frequencies regardless of whether a pipeline operation by a flow control is stopped or not, without significantly increasing a processing latency even if a clock frequency is decreased, and in response to performance requests for a processing throughput. Among P clocks (P is a positive integer), the phases of which are delayed in the order from the first clock to the P-th clock, for example, among six clocks (P0 to P5), two consecutive clocks, the phases of which are delayed from each other by a predetermined phase, are assigned to a plurality of stages, for example, five stage pipeline buffers (32a to 32e), in the order from the previous stage to the next stage, and also are assigned so that one clock signal having an identical phase is shared between adjacent two pipeline buffers. For example, the first stage pipeline buffer (32a) is operated by two of the clock (P0) and the next clock (P1) and the second stage pipeline buffer (32b) is operated by two of the same clock (P1) as supplied to the first stage and the clock (P2) next to the clock (P1).
Inventors:
SHIBAYAMA ATSUFUMI (JP)
Application Number:
PCT/JP2010/003059
Publication Date:
January 13, 2011
Filing Date:
April 28, 2010
Export Citation:
Assignee:
NEC CORP (JP)
SHIBAYAMA ATSUFUMI (JP)
SHIBAYAMA ATSUFUMI (JP)
International Classes:
H03K5/00; G06F1/06; H03K5/15
Foreign References:
| JPH04152432A | 1992-05-26 | |||
| JPS63201725A | 1988-08-19 | |||
| JPS61250571A | 1986-11-07 |
Attorney, Agent or Firm:
IEIRI, Takeshi (JP)
家入健 (JP)
家入健 (JP)
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