PIXEL CIRCUIT AND DISPLAY DEVICE

WIPO Patent Application WO/2011/055573

A1

Disclosed is a display device equipped with a pixel circuit having a low-mobility transistor, in which the power consumption is reduced without causing the decrease in aperture ratio. A liquid crystal capacitance element (Clc) is intercalated between a pixel electrode (20) and a counter electrode (80). An internal node (N1) is formed by the pixel electrode (20), one end of a first switching circuit (22), one end of a second switching circuit (23), and a first terminal of a second transistor (T2). The other end of the first switching circuit (22) is connected to a source line (SL). The other end of the second switching circuit (23) is connected to a voltage supply line (VSL), and is composed of a series circuit of a transistor (T1) and a transistor (T3). An output node (N2) is formed by a control terminal of the transistor (T1), a second terminal of the transistor (T2) and one end of a boost capacitance element (Cbst). The other end of the boost capacitance element (Cbst) is connected to a selection line (SEL), the control terminal of the transistor (T2) is connected to a reference line (REF), and the control terminal of the transistor (T3) is connected to the selection line (SEL) through a delay circuit (31).

YAMAUCHI YOSHIMITSU

PCT/JP2010/062319

May 12, 2011

July 22, 2010

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SHARP KK (JP)
YAMAUCHI YOSHIMITSU

G09G3/36; G02F1/133; G09G3/20; G09G3/30

JP2007502068A	2007-02-01
JPS6169283A	1986-04-09
JPS6174481A	1986-04-16
JP2005018088A	2005-01-20
JP2004212924A	2004-07-29
JP2006343563A	2006-12-21
JP2007334224A	2007-12-27

MASAKI YOSHIFUMI (JP)
Yoshifumi Masaki (JP)

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