Title:
POWER AMPLICATION DEVICE
Document Type and Number:
WIPO Patent Application WO/2020/203506
Kind Code:
A1
Abstract:
This power amplifier (100 has: a first semiconductor chip (103) that has a first main surface (301) and a second main surface (302); a first field effect transistor; a first drain finger part (21), a plurality of first gate finger parts (11), and a source finger part (31); a sub-mount substrate (101) having a third main surface (303) and a fourth main surface (304); and a first filled via (108) provided so as to penetrate from the third main surface (303) to the fourth main surface (304). In plan view, the first filled via (108) is rectangular. The long-side direction of the first filled via (108) is provided so as to be parallel to the long-side direction of the plurality of first gate finger parts (11). In plan view, the first filled via (108) is provided at a position overlapping some of one first gate finger part (11) from among the plurality of first gate finger parts (11).
Inventors:
OHHASHI KAZUHIKO
KAMITANI MASATOSHI
YAMAMOTO KOUKI
KAMITANI MASATOSHI
YAMAMOTO KOUKI
Application Number:
PCT/JP2020/013167
Publication Date:
October 08, 2020
Filing Date:
March 24, 2020
Export Citation:
Assignee:
PANASONIC SEMICONDUCTOR SOLUTIONS CO LTD (JP)
International Classes:
H01L23/36; H03F1/30; H03F3/213
Domestic Patent References:
| WO2017094589A1 | 2017-06-08 |
Foreign References:
| JP2003008470A | 2003-01-10 | |||
| JP2013123031A | 2013-06-20 | |||
| JP2005026368A | 2005-01-27 | |||
| JP2006229218A | 2006-08-31 | |||
| JP2015065233A | 2015-04-09 | |||
| JP2007266539A | 2007-10-11 | |||
| JP2017228966A | 2017-12-28 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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