Title:
POWER AMPLIFYING CIRCUIT, HIGH FREQUENCY CIRCUIT, AND COMMUNICATION DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/131147
Kind Code:
A1
Abstract:
The present invention improves the power addition efficiency. A second transistor (Q2) has a second base connected to the first collector of a first transistor (Q1). A third transistor (Q3) has a third base connected to the first collector of the first transistor (Q1) and has a third collector connected to the second collector of the second transistor (Q2). A second bias circuit (5) includes a fifth transistor (50) connected to the second base of the second transistor (Q2). A third bias circuit (6) includes a sixth transistor (60) connected to the third base of the third transistor (Q3). A first current limiting circuit (7) has a seventh transistor (70), a first collector resistor (Rc1) and a first base resistor (Rb1). A second current limiting circuit (8) has an eighth transistor (80), a second collector resistor (Rc2) and a second base resistor (Rb2).
Inventors:
TAHARA KENJI
SHIMAMOTO KENICHI
TANAKA YUSUKE
SHIMAMOTO KENICHI
TANAKA YUSUKE
Application Number:
PCT/JP2020/031128
Publication Date:
July 01, 2021
Filing Date:
August 18, 2020
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H03F1/02; H03F3/24
Foreign References:
| JP2019176454A | 2019-10-10 |
Attorney, Agent or Firm:
HOKUTO PATENT ATTORNEYS OFFICE (JP)
Download PDF:
Previous Patent: INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM
Next Patent: RFIC MODULE AND RFID TAG
Next Patent: RFIC MODULE AND RFID TAG