MANUFACTURE THEREOF

Field of the Invention

This invention relates to a semiconductor field effect transistor device, for example, of the power type comprising a source, a drain, a channel and a gate stack. The present invention also relates to a method of manufacture of a semiconductor field effect transistor device, and a use of a protective layer.

Background of the Invention

In the field of semiconductor field effect transistor devices, power Metal Oxide Field Effect Transistor

(MOSFET) devices are known to comprise a number of different structural arrangements, but common to most power MOSFET device structures is a substrate, an epitaxial layer having a source spaced apart from a drain therein. The epitaxial layer also comprises a doped channel region adjacent the source and a gate stack is disposed upon the doped channel region, and overlies part of the source region and, optionally, the drain as well.

A feature of power MOSFET devices is the graduated nature of the doping of the doped channel region, starting with a high level of doping nearest the source that gradually reduces as the doped channel region extends away from the source.

A requirement of power MOSFET devices is reliability . In this respect, with respect to a so-called "threshold

voltage", V _TH , of the power MOSFET device, the threshold voltage must remain substantially constant over the lifetime of a given MOSFET device and must not be subject to "drift".

However, power MOSFET devices are known to suffer from the above mentioned threshold voltage drift. This drift is understood to be caused by contaminants, for example hydrogen, such as hydrogen atoms and/or ions, reaching the highly doped part of the doped channel region nearest the source diffusion. The presence of the contaminants at the highly doped part of the doped channel region serve to reduce the effective doping level at the highly doped part of the doping channel, thereby reducing a voltage inversion that needs to take place at the highly doped part of the doped channel region when the device is in use. Consequently, the threshold voltage of the power MOSFET devices drift over the lifetime of the device from an original threshold voltage value.

Statement of Invention

According to the present invention, there is provided a semiconductor field effect transistor device, a method of manufacturing a semiconductor field effect transistor device as set forth in the claimed herein.

Brief Description of the Drawings

At least one embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIGs. 1 to 8 are schematic diagrams of layers of a semiconductor power MOSFET device provided or formed to yield a part-device, FIGs. 2 to 4 being represented to a different scale with respect to FIGs. 5 onwards;

FIGs. 9 and 10 are schematic diagrams of a composite spacer constituting an embodiment of the invention and formed on the part-device of Figure 8; and

FIG. 11 to 16 are schematic diagrams of processing steps subsequent to the formation of the composite spacer.

Description of Preferred Embodiments

Referring to FIG. 1, a wafer 100 of starting material is either grown or procured for fabricating a plurality of N-type power MOSFET devices. The wafer comprises a highly N-doped substrate 102, upon which an N-type epitaxial layer 104 is grown. The substrate 102 is a <100> substrate doped with Arsenic to yield a resistivity of between about 4.0 to 5.5 mΩ.cm. A backseal 106 is formed on a backside of the substrate 102, the backseal 106 comprising a lμm polysilicon (PoIySi) backseal layer 108 disposed adjacent an 8000A Low Temperature Oxide (LTO) layer 110. An initial oxide layer 112 of silicon dioxide (Siθ ₂ ) is then grown on top of the epitaxial layer 104 to a depth, in this example, of 6750A.

Thereafter (FIG. 2) , using a known masking technique, an active area 114 is defined using photoresist (not shown) and a part of the initial oxide layer 112 is removed in the active area 114 using a two-step etching technique comprising a dry, plasma, etch step and a wet etch step.

Both these etching techniques are known to those skilled in the art and so will not be described further. Once the active area 114 has been etched, the photoresist is subsequently removed.

Referring to FIG. 3, a, in this example 400A, gate oxide layer 116 formed from Silicon Dioxide is then grown in the active area 114, followed by a deposition of another PoIySi layer 118 over the wafer 100. In this example, the another PoIySi layer 118 is 6500A thick. The PoIySi layer 118 is then subjected to an N-blanket implantation 120 of Phosphorous ions.

Turning to FIG. 4, an Oxide-Nitride-Oxide (ONO) stack is then formed adjacent the another PoIySi layer 118 by growing a polyoxide layer 122 adjacent the PoIySi layer 118, followed by deposition of a 450A thick Silicon Nitride (SIaN ₄ ) layer 124 using a Low Pressure Chemical Vapour Deposition (LPCVD) technique. In this example, the polyoxide layer is about 300A thick. An Inter-Layer Dielectric (ILD) layer 126, in this example a 6000A Tetra Ethyl OrthoSilicate (TEOS) layer, is then deposited on the Silicon Nitride layer 124.

Although not shown in FIG. 5, a photoresist gate mask is deposited to define a gate stack 128. Thereafter, a two- stage anisotropic etching process is carried out. Firstly, an exposed part of the ONO stack is removed in an oxide reactive ion plasma etcher. The photoresist layer is then stripped away and the wafer 100 subjected to a cleaning stage. A now-exposed part of PoIySi layer 118 is then etched away in a PoIySi reactive ion plasma etcher in order to obtain a vertical stack profile

comprising a part of the ONO stack in addition to the PoIySi layer 118, and constituting the gate stack 128. Etching of the exposed part of the PoIySi layer 118 is stopping at the gate oxide layer 116, and once again, the wafer 100 is then subjected to another cleaning stage.

The etched areas in combination with the gate stack 128 constitute an active region 130. The etching carried out in relation to FIG. 5 yields an edge cell 132 and a central cell 134. As is known in the art, a MOSFET device comprises many edge and central cells (not shown) , but for the purpose of simplicity of description and hence clarity, only one of each is shown.

Referring to FIG. 6, the active region 130 is subjected to an ion implantation processing stage 136, so that the epitaxial layer 104 beneath the edge cell 132 and the central cell 134 are implanted with positive boron ions 138 as a first stage to a formation of a first P-type High Voltage (PHV) region and a second PHV region (not shown in FIG. 6) . During the implantation of the boron ions 138, the gate oxide layer 116 serves as a screen oxide for the PHV ionic implantation .

Turning to FIG. 7, as a second stage to the formation of the first and second PHV "body" regions 140, 142, a PHV drive stage follows the implantation stage 136, consisting of exposing the wafer 100 to a thermal cycle, in this example for 130 minutes at a temperature of 1080 ⁰ C.

Another masking technique is then employed (FIG. 8), whereby a layer of photoresist 144 is patterned to expose

a peripheral region 146 of the central cell 134. The layer of photoresist 144 is then subjected to an N ⁺ implantation stage 145, the exposed peripheral region 146 of the central cell 134 permitting the implantation of Arsenic (As) ions 148 into the second PHV region 142. Thereafter, the layer of photoresist 144 is stripped away.

Referring to FIG. 9, a thin nitride layer 150 is then deposited on the wafer 100 using a LPCVD technique. In this example, the nitride layer 150 is formed from Silicon Nitride and is 300A thick. Although, in this example, the nitride layer 150 is 300A thick, the nitride layer 150 can be between 150A thick and IOOOA thick. In other embodiments, the nitride layer 150 can be between 300A and 600A thick. Further, the use of silicon nitride to form the nitride layer is only one type of protective layer and it should be appreciated that the function of the nitride layer 150 is to block at least one contaminant, for example hydrogen, and so any suitable material can be used that can block the passage of the at least one contaminant, for example hydrogen, therethrough. In this example in relation to silicon nitride, silane (SiH ₄ ) is used by the LPCVD technique at a temperature of between about 700°C and 750°C. However, whilst the silane, of course, contains hydrogen, the silicon-hydrogen bonds created by use of the LPCVD technique are strong and do not result in the presence of free hydrogen. A TEOS oxide layer 152 is then deposited adjacent the nitride layer 150 using a Low Temperature Oxide (LTO) deposition technique. In this example, the TEOS oxide layer 152 is 6000A thick.

Once formed, the nitride layer 150 and the TEOS oxide layer 152 are anisotropically etched (FIG. 10) in an oxide reactive ion etcher to yield composite spacers 154. Consequently, in the present example, the thickness of the nitride layer 150 is sufficiently thin to avoid any protuberances or cavities being formed that can affect the curved profile of the spacer 154.

A horizontal portion 156 of the nitride layer 150 serves as a protective layer against at least one type of contaminant as will be described in more detail later herein. In this example, the nitride layer 150 has a vertical portion 158 that also protects the gate stack 128.

Referring to FIG. 11, a blanket implantation stage 160 is then carried out to implant boron ions 162 into the first and second PHV regions 140, 142 via the edge cell 132 and the central cell 134, respectively. This implantation stage 160 is carried out in order to fix the potential of the PHV body regions 140, 142 and improve the so-called undamped inductive switching behaviour of the device. Turning to FIG. 12, the implanted arsenic ions 148 and the implanted boron ions 162 are subjected to a thermal cycle of 30 minutes at 900°C, and constituting an anneal stage. This stage is known in the art and so, for conciseness, will not be described further. As a result of the above anneal stage, the first PHV region 140 of the edge cell 132 only comprises a p ⁺ region 164. With respect to the central cell 134, the second PHV region 142 comprises a p ⁺ region 164 therein and an annular n- type Source/Drain (n s/d) region 166 bridging the p ⁺ region beneath the central cell 134. In should be

understood that the n s/d region 166 constitutes a source of one central cell of the device.

A region adjacent the surface of and in the second PHV region 142 between the peripheries of the second PHV region 142 and the n s/d region 166 constitutes a channel region 167. Due to the nature of the formation of the second PHV region 142, the level of doping of the channel region 167 at a first end thereof adjacent the source 166 is higher than at a second end thereof adjacent the periphery of the second PHV region 142. In this respect, the level of doping from the first end of the channel region 167 to the second end of the channel region 167 decreases gradually, i.e. is graduated. In the present example, the first end of the channel region 167 is very close to the edge of the gate stack 128, such as 0.13μm therefrom. However, the horizontal part 156 of the nitride layer 150 overlaps a substantial part of the source 166, thereby providing protection to the channel region 167, especially the first end of the channel region 167 from the at least one contaminant mentioned above, for example, hydrogen.

A further photoresist layer 170 (FIG. 13) is then deposited over an uppermost surface of the wafer 100 using a known masking technique. Although not shown in FIG. 13 due to the gate contact (also not shown) being at the periphery of the active region 130, the photoresist layer 170 comprises apertures that, when the device thus far is subjected to a reactive ion etching stage, result in openings (not shown) being formed for the deposition of metal therein so as permit the connection of a source pad (not shown) and a gate stack

pad (not shown) to pads of a device package frame (not shown) by aluminium wires. Once etched, the photoresist layer 170 is stripped away and an aluminium-silicon layer 172 is deposited (FIG. 14) using a sputtering technique known in the art. The aluminium-silicon layer 172 is deposited to a thickness of 4μm. Thereafter, the aluminium-silicon layer 172 is covered with another photoresist layer (not shown) using a known masking technique, and then etched in a spray etcher. In order to obtain a good metal-silicon alloy, the wafer undergoes a sinter step in a low temperature furnace, in this example, at a temperature of 390 ⁰ C for 30 minutes.

Referring to FIG. 15, a passivation nitride-above-oxide stack 174 comprising a layer of Silicon Nitride on Undoped Silicon Glass (USG) is deposited using a Plasma Enhanced Chemical Vapour Deposition (PECVD) system and, after a photomasking technique, etched in a oxide reactive ion etcher. However, in another embodiment, the passivation stack 174 can be replaced with one or more layers of material suitable for performing the role of passivation that do not introduce, or alternatively, minimise the introduction of free hydrogen into the device. In this respect, the passivation stack comprises a predetermined amount of free hydrogen, free hydrogen being hydrogen atoms or ions that are weakly bonded within the passivation stack 174 and are freed or released from their respective bonds by energy imparted to break the bonds through mechanical stresses. In this example, the hydrogen is weakly bonded to silicon to form silicon-hydrogen bonds. The predetermined amount of free hydrogen should not be sufficient to cause drift of a

threshold voltage of the power MOSFET device when the device is in use.

After provision of the passivation stack 174 (FIG. 16) , the PoIySi backseal layer 108 and LTO backseal layer 110 are removed using a backgrinding technique known in the art until the wafer 100 is about 250μm thick, and a

Titanium-Nickel-Silver alloy layer 176 is deposited on the back-side of the substrate 102 using a known metallisation technique to form a drain.

The above example is of an N-type epitaxial power MOSFET. It should therefore be appreciated that the above example can be modified to create a P-type epitaxial MOSFET device. Moreover, whilst the above example has been described in the context of a power MOSFET device, the provision of the protective layer described above can be applied to other Field Effect Transistor (FET) devices requiring protection of the channel region from contaminants, for example MOSFETs, i.e. non-power MOSFETs.

It is thus possible to provide a semiconductor field effect transistor device and method of manufacture thereof that prevents contamination of the channel region, thereby preserving a level of voltage inversion at the highly doped part of the channel region. Consequently, drift of the threshold voltage is obviated or at least mitigated and the useable lifetime, and also reliability, of the device is extended. Further, the drain-source on-resistance (R _DS (on) ) is reduced. Additionally, device sizes can be reduced, thereby increasing the level of integration of such devices,

because the decrease in a path size from a source of contaminants to the channel region is immaterial due to the presence of the protective layer. Also, by selecting as a passivation layer a material that releases less hydrogen than other known passivation layers or substantially no hydrogen, the performance of the channel region and hence the device is improved.