Title:
POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR POWER SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/087920
Kind Code:
A1
Abstract:
This power semiconductor device is provided with a substrate and a semiconductor element bonded to a first surface of the substrate using a sinterable metal bonding material. The substrate has, disposed on the first surface thereof, a plurality of dimples that are formed in an area located on the outer side of an area immediately below a heat-generating section of the semiconductor element. The sinterable metal bonding material is supplied on the substrate after the dimples are formed, and then heat and pressure are applied so as to bond the semiconductor element to the substrate.
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Inventors:
YABUTA KOHEI (JP)
YAMADA TAKAYUKI (JP)
MURAMATSU YUYA (JP)
BESSHI NORIYUKI (JP)
SUGI YUTARO (JP)
HARUNA HIROAKI (JP)
FUKU MASARU (JP)
FUJITA ATSUKI (JP)
YAMADA TAKAYUKI (JP)
MURAMATSU YUYA (JP)
BESSHI NORIYUKI (JP)
SUGI YUTARO (JP)
HARUNA HIROAKI (JP)
FUKU MASARU (JP)
FUJITA ATSUKI (JP)
Application Number:
PCT/JP2018/039659
Publication Date:
May 09, 2019
Filing Date:
October 25, 2018
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H01L21/52; H01L23/12; H01L25/07; H01L25/18
Foreign References:
| JP2010030280A | 2010-02-12 | |||
| JP2015035459A | 2015-02-19 | |||
| JP2014138042A | 2014-07-28 | |||
| JP2013165117A | 2013-08-22 | |||
| JP2017108192A | 2017-06-15 |
Attorney, Agent or Firm:
SOGA, Michiharu et al. (JP)
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