Title:
POWER SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2017/119226
Kind Code:
A1
Abstract:
The present invention addresses the problem that, during clamping of molds, an excessive stress may be applied to a bonding portion between a substrate and an input/output terminal, possibly causing the bonding portion to become peeled or the substrate to crack.
A lower surface electrode of a power semiconductor element 11 is connected to a first wiring layer 12 on a lower surface of the power semiconductor element 11 via a bonding material 13. An upper surface electrode 14 of the power semiconductor element 11 is connected to a second wiring layer 15 on an upper surface via the bonding material 13. A second main terminal 16 electrically connected to the upper surface electrode 14 of the power semiconductor element 11 is connected to the second wiring layer 15 via the bonding material 13, and positioned in contact with a third wiring layer 24 (spacer) disposed side by side with the first wiring layer 12 on the lower surface. An insulating layer 26 is laminated on the opposite side of each of the first wiring layer 12 to the third wiring layer 24 from the respective bonding materials 13, and a heat dissipating layer 27 is laminated on the insulating layer 26.
Inventors:
SUWA TOKIHITO (JP)
FUNABA SEIJI (JP)
FUNABA SEIJI (JP)
Application Number:
PCT/JP2016/086291
Publication Date:
July 13, 2017
Filing Date:
December 07, 2016
Export Citation:
Assignee:
HITACHI AUTOMOTIVE SYSTEMS LTD (JP)
International Classes:
H01L25/07; H01L23/28; H01L23/29; H01L25/18
Domestic Patent References:
| WO2012096066A1 | 2012-07-19 |
Attorney, Agent or Firm:
TODA Yuji (JP)
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