DESCRIPTION

POWER SUPPLY CIRCUIT AND METHOD FOR CONTROLLING THE

SAME

TECHNICAL FIELD

The present invention relates to a power supply circuit configured to supply power to a load for stably driving the load and to a method for controlling an operation of the power supply circuit.

BACKGROUND ART

When a voltage higher than a power source voltage is required, a DC-DC converter using an inductor has been conventionally used as a power supply circuit. DC-DC converters have been used for many applications since a voltage at a desired level can be generated and power can be efficiently supplied to a load which consumes a large amount of current. However, it is difficult to downsize the DC-DC converter since components such as a transformer and a coil are required. Therefore, it has been impossible to include all components of the DC-DC converter in a semiconductor integrated circuit In view of these problems, a charge pump

circuit has been sometimes used as a power supply circuit since the charge pump circuit can be downsized and is capable of high efficiencies. However, since the charge pump circuit raises an output voltage by adding a voltage of a capacitor charged by a voltage of a DC power source, the output voltage of the charge pump circuit is largely dependent on the power source voltage. Further, when a battery is used as the DC power source, the output voltage of the charge pump circuit decreases in accordance with a drop of a battery voltage, by a voltage level obtained by multiplying the drop in the battery voltage with a raising ratio of the voltage. As a result, the output voltage of the charge pump circuit rapidly decreases.

In order to avoid such effects of a change of the power source voltage, the following three methods have been suggested. As a first method, as shown in FIG. 5, a power source voltage VCC is controlled to be a constant voltage by a voltage regulator 101 and inputted to a charge pump circuit 102 to be raised. The raised voltage is then supplied to a load 110 (for example, see Patent Document 1) . As a second method, as shown in FIG. 6, an input power source voltage VCC is inputted to the

charge pump circuit 102 to be raised. The raised voltage is then inputted to the voltage regulator 101 and controlled as a constant voltage, and supplied to the load 110. As a third method, as shown in FIG. 7, when an output voltage Vout of a charge pump circuit becomes at a predetermined detection voltage or higher, each on-period of a transistor MlOl, which connects a flyback capacitor Cl in the charge pump circuit and a catch-back capacitor Cout provided outside the charge pump circuit, is forcibly shortened to obtain a constant output voltage.

[Patent Document 1] Japanese Patent Application Publication No. 2006-320158

An output voltage can be stabilized with stable ripple amplitude by the first and second methods. In these cases, however, there is required a voltage regulator which has a large output driver through which a maximum output current of the charge pump circuit can flow. Therefore, there is a problem in that chip size is increased.

By the third method, a constant voltage can be stably outputted by only monitoring an output voltage of the charge pump circuit and when the output voltage of the charge pump circuit becomes a predetermined level or higher, feeding back a

detected signal to a clock unit which controls ON/OFF of the charge pump circuit. However, since each on- period of the charge pump circuit is forcibly shortened, there is a problem in that a ripple amplitude of the output voltage becomes larger.

DISCLOSURE OF INVENTION

The present invention has been made in view of the above problems and it is an object of at least one embodiment of the present invention to provide a power supply circuit which can output a constant voltage required for stably driving a load regardless of a variation of a power source voltage, by optimally controlling a gate voltage of a transistor included in a charge pump circuit, and to provide a method for controlling an operation of the power supply circuit.

According to one aspect of the invention, a power supply circuit includes a charge pump circuit configured to raise a voltage inputted from an input terminal and supply the raised voltage from an output terminal to a given load and a control circuit unit. The charge pump circuit includes a fly-back capacitor configured to store a charge of the voltage inputted from the input terminal and an output transistor

connected between one terminal of the fly-back capacitor and the output terminal of the charge pump circuit. The control circuit unit receives a reference voltage and the voltage outputted from the charge pump circuit and is configured to generate a proportional voltage proportional to the voltage outputted from the charge pump circuit and output a voltage to control the output transistor depending on a difference between the proportional voltage and the reference voltage so that the proportional voltage has the same voltage level as the reference voltage.

According to another aspect of the invention, there is provided a method for controlling an operation of a power supply circuit including a charge pump circuit configured to raise a voltage inputted from an input terminal and supply the raised voltage from an output terminal to a given load. The charge pump circuit includes a fly-back capacitor configured to store a charge of the voltage inputted from the input terminal and a transistor connected between one terminal of the fly-back capacitor and the output terminal of the charge pump circuit. The method includes steps of controlling the transistor so that a voltage proportional to the raised voltage becomes the same level as a reference voltage and

keeping the raised voltage constant based on said controlling of the transistor for provision to the load.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing an example of a power supply circuit and an example of clock signals of a first embodiment of the present invention.

FIG. 2 is a timing chart showing an example of a relationship between an output signal AMPOUT and an output voltage Vout of the power supply circuit shown in FIG. 1.

FIG. 3 is a diagram showing another example of a power supply circuit and an example of clock signals of the first embodiment of the present invention.

FIG. 4 is a timing chart showing an example of a relationship between an output signal AMPOUT and an output voltage Vout of the power supply circuit shown in FIG. 3.

FIG. 5 is a diagram showing an example of a conventional power supply circuit.

FIG. 6 is a diagram showing another example of a conventional power supply circuit. FIG. 7 is 'a timing chart showing an example

of a relationship between an operation of a transistor MlOl and an output voltage Vout in a conventional power supply circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention is described in detail based on the embodiment illustrated in the drawings. (First embodiment)

FIG. 1 is a diagram showing an example of a power supply circuit of a first embodiment of the present invention. In a power supply circuit 1 shown in FIG. 1, a power source voltage VCC inputted to an input terminal IN is raised and a predetermined constant voltage is generated. The generated constant voltage is outputted as an output voltage Vout from an output terminal OUT to a load 10. In this manner, power is supplied to the load 10.

The power supply circuit 1 includes a charge pump circuit 2; a reference voltage generating circuit 3 capable of generating and outputting a predetermined reference voltage Vref; resistors Rl and R2 for detecting an output voltage, which are capable of dividing the output voltage Vout and generating and outputting a divided voltage Vfb; an error amplifier circuit 4, and a catch-back capacitor

Cout . The charge pump circuit 2 includes PMOS transistors Ml through M3, an NMOS transistor M4, and a flyback capacitor Cl. The error amplifier circuit 4 includes an operational amplifier circuit 11, a constant current source 12, and an NMOS transistor Mil.

The PMOS transistor M3 serves as an output transistor, the resistors Rl and R2 serve as a proportional voltage generating circuit unit, the error amplifier circuit 4 serves as an error amplifier circuit unit, the NMOS transistor Mil serves as a first transistor, and the constant current source 12 and the NMOS transistor Mil serve as an output circuit. Further, FIG. 1 shows an example in which the PMOS transistors Ml through M3, the NMOS transistor M4, the reference voltage generating circuit 3, the error amplifier circuit 4, and the resistors Rl and R2 are integrated in one IC. The IC includes the input terminal IN, an output terminal OUT, and connecting terminals ClP and ClM.

The PMOS transistor Ml is connected between the input terminal IN and the connecting terminal ClP. The PMOS transistor M2 is connected between the input terminal IN and the connecting terminal ClM. The flyback capacitor Cl is connected between the

connecting terminals ClP and ClM. The PMOS transistor M3 is connected between the connecting terminal ClP and the output terminal OUT. The NMOS transistor M4 is connected between the connecting terminal ClM and ground potential. The catch-back capacitor Cout is connected between the output terminal OUT and ground potential. The resistors Rl and R2 are connected in series between the output terminal OUT and ground potential. The divided voltage Vfb is outputted from a connection between the resistors Rl and R2 and inputted to an inverting input terminal of the operational amplifier circuit 11.

The reference voltage Vref is inputted to a non-inverting input terminal of the operational amplifier circuit 11. An output terminal of the operational amplifier circuit 11 is connected to a gate of the NMOS transistor Mil. The constant current source 12 and the NMOS transistor Mil are connected in series between the power source voltage VCC and ground potential. A connection between the constant current source 12 and the NMOS transistor Mil, which serves as an output terminal of the error amplifier circuit 4, is connected to a gate of the PMOS transistor M3. A clock signal φl, a clock

signal φ2, and an inverted signal φlB which is an inverted clock signal φl are inputted to a gate of the PMOS transistor Ml, a gate of the PMOS transistor M2, and a gate of the NMOS transistor M4 , respectively. Note that the clock signals φl and φ2 are expressed by rectangular waveforms with timings as shown in a lower diagram of FIG. 1.

With such a configuration, the PMOS transistors Ml, M2, and the NMOS transistor M4 are turned ON/OFF in accordance with the clock signals φl and φ2. The error amplifier circuit 4 controls an operation of the PMOS transistor M3 so that the divided voltage Vfb has the same level as the reference voltage Vref. In this manner, the error amplifier circuit 4 controls on-resistance of the PMOS transistor M3 so that the output voltage Vout becomes constant at a predetermined level.

FIG. 2 is a timing chart showing an example of a relationship between an output signal AMPOUT of the error amplifier circuit 4, which is inputted to the gate of the PMOS transistor M3, and the output voltage Vout. The operation of the power supply circuit 1 shown in FIG. 1 is described in more detail with reference to FIG. 2. When the clock signal φl is at a low level,

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the PMOS transistor Ml and the NMOS transistor M4 are turned on and become conductive. Since the clock signal φ2 is at a high level at this time, the PMOS transistor M2 is turned off and becomes non- conductive. In this case, the output voltage Vout is higher than a set voltage as shown in FIG. 2. Therefore, the operational amplifier circuit 11 turns off the NMOS transistor Mil to be non-conductive in order to drop the output voltage Vout to the set voltage. Thus, the output signal AMPOUT of the error amplifier circuit 4 has a voltage capable of turning off the PMOS transistor M3 to be non-conductive. In view of these, the flyback capacitor Cl is charged by the power source voltage VCC. Moreover, when the clock signal φl is at a high level, the PMOS transistor Ml and the NMOS transistor M4 are turned off and become non- conductive. As the clock signal φ2 is at a low level at this time, the PMOS transistor M2 is turned on and becomes conductive. As shown in FIG. 2, the output voltage Vout is lower than the set voltage. Therefore, the operational amplifier circuit 11 turns on the NMOS transistor Mil and controls on-resistance of the NMOS transistor Mil in order to raise the output voltage Vout to the set voltage. As a result,

the output signal AMPOUT of the error amplifier circuit 4 has a voltage capable of turning on the PMOS transistor M3. The error amplifier circuit 4 controls a gate voltage of the PMOS transistor M3 and controls on-resistance of the PMOS transistor M3 so that the output voltage Vout becomes a predetermined voltage .

By repeating these operations in synchronization with a frequency of a clock signal for driving the charge pump circuit 2, the gate voltage of the PMOS transistor M3 is controlled and the on-resistance of the PMOS transistor M3 is optimized. In this manner, the output voltage Vout can be stabilized without making a ripple amplitude of the output voltage Vout larger.

FIG. 3 is a diagram showing another example of a power supply circuit of the first embodiment of the invention. In FIG. 3, components that are the same or similar to those in FIG. 1 are denoted by the same reference numerals and their descriptions are omitted here. Only the differences between FIGS. 1 and 3 are described below.

FIG. 3 is different from FIG. 1 in that an NMOS transistor M12 and a PMOS transistor M13 are additionally provided. The NMOS transistor M12

serves as a second transistor and the PMOS transistor M13 serves as a third transistor. Further, the PMOS transistors Ml through M3 and M13, the NMOS transistors M4 and M12, the reference voltage generating circuit 3, the error amplifier circuit 4, and the resistors Rl and R2 are integrated in one IC in this example.

The NMOS transistor M12 is connected between the output terminal of the operational amplifier circuit 11 and ground potential. The clock signal φ2 is inputted to a gate of the NMOS transistor M12. Further, the PMOS transistor M13 is connected in parallel to the constant current source 12. An inversion signal φ2B which is an inverted clock signal φ2 is inputted to a gate of the PMOS transistor M13.

In this manner, the output signal AMPOUT of the error amplifier circuit 4 can be rapidly raised or dropped and the output signal AMPOUT in FIG. 2 can have a waveform as shown in FIG. 4. In FIG. 3, only one of the NMOS transistor M12 and the PMOS transistor M13 may be provided.

In the power supply circuit of the first embodiment of the present invention, a charge stored in the flyback capacitor Cl is pumped into the catch-

back capacitor Cout by the PMOS transistor M3 which connects the connecting terminal ClP connected to one terminal of the flyback capacitor Cl and the output terminal OUT connected to one terminal of the catch- back capacitor Cout, thereby the power source voltage VCC is raised. To control the output voltage Vout to be constant, the raised output voltage Vout is fed back through a feed-back circuit, which is formed of the resistors Rl and R2 and connected to the output terminal OUT, to the error amplifier circuit 4 which controls the gate voltage of the PMOS transistor M3, thereby the on-resistance of the PMOS transistor M3 is controlled. As a result, a constant voltage required for stably driving a load can be outputted regardless of a change of the power source voltage.

According to the power supply circuit of the present invention and the method for controlling the operation of the power supply circuit of the present invention, the operation of the output transistor which is included in the charge pump circuit and connected between one terminal of the flyback capacitor included in the charge pump circuit and the output terminal of the charge pump circuit, is controlled so that the proportional voltage which is in proportion to the output voltage outputted from

the output terminal becomes the same level as a predetermined reference voltage. As a result, the output voltage of the charge pump circuit is controlled to be a constant voltage and supplied to the load. In this manner, a constant voltage required for stably driving the load can be outputted regardless of the change of the power source voltage.

Further, instead of using a regulator having a large output driver to stably output the voltage, which increases the chip size, a regulator circuit having an output driver served by a transistor which connects one terminal of the flyback capacitor and the output terminal of the charge pump circuit is used among transistors included in the charge pump circuit. As a result, the increase of the chip size can be prevented.

Further, instead of employing the conventional method to shorten each on-period of the charge pump circuit to stabilize the output voltage, which increases a ripple amplitude, a gate voltage of a transistor which transmits a charge stored in the flyback capacitor to the catch-back capacitor is controlled in accordance with the level of the output voltage. As a result, the on-resistance of the transistor is controlled. In this manner, a stable

output voltage can be obtained without increasing the ripple amplitude.

The present application is based on Japanese Priority Application No. 2008-005844 filed on January 15, 2008, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference .