ENCODING/DECODING PROCESSOR AND WIRELESS COMMUNICATION APPARATUS

WIPO Patent Application WO/2012/108411

A1

[Problem] To provide an encoding/decoding processor or the like that can quickly perform various encoding/decoding processes in a plurality of wireless communication systems and that can be made by use of a simple circuit configuration. [Solution] An encoding/decoding processor (100) includes a coprocessor (11) that is dedicated to encoding and decoding processes. The coprocessor (11) comprises: a parameter register (60) that stores externally given operation modes and the settings of generation polynomials; and a calculation circuit (22a) that operates on the basis of the operation modes and the generation polynomials and that performs calculations, which are required for the encoding and decoding processes, by a plurality of bits per cycle in a parallel manner. The coprocessor (11) further comprises memory controllers (20, 21), which include: address generator circuits (30, 40) for outputting the addresses of the storage devices; FIFO circuits (31, 41) for temporarily storing data; and data packing circuits (32, 42) for making up predetermined numbers of bits of data for output.

TAKEUCHI TOSHIKI (JP)
IGURA HIROYUKI (JP)

PCT/JP2012/052696

August 16, 2012

February 07, 2012

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NEC CORP (JP)
TAKEUCHI TOSHIKI (JP)
IGURA HIROYUKI (JP)

H03M13/29; H04L1/00

JP2000209102A	2000-07-28
JPH11274942A	1999-10-08
JPH0918354A	1997-01-17
JP2000148975A	2000-05-30

TAKAHASHI ISAMU (JP)
Isamu Takahashi (JP)

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