PROGRAMMABLECONSTANTPOWER FOLDBACK

Technical Field

[0001] This disclosure relates to power supply systems, and more particularly, to circuitry and methodology for providing a foldback current limit in a power supply system, such as a Power over Ethernet (PoE) system.

Background Art

[0002] Traditionally, network devices such as EP phones, wireless LAN access points, personal computers and Web cameras have required two connections: one to a LAN and another to a power supply system. A PoE system eliminates the need for additional outlets and wiring to supply power to network devices. Instead, power is supplied over Ethernet cabling used for data transmission.

[0003] The PoE system must comply with the IEEE 802.3af standard that defines delivering power over unshielded twisted-pair Ethernet wiring from a PSE to a PD located at opposite sides of a link. As defined in the IEEE 802.3af standard, PSE and PD are iion-data entities allowing network devices to supply and draw power using the same generic cabling as is used for data transmission. A PSE is the equipment electrically specified at the point of the ^' physical connection to the cabling, that provides the power to a link. A PSE is typically associated with an Ethernet switch, router, hub or other network switching equipment or midspan device. A PD is a device that is either drawing power or requesting power. PDs may be associated with such devices as digital EP telephones, wireless network access points, . PDA or notebook computer docking stations, cell phone chargers and HVAC thermostats. [0004] The main functions of the PSE are to search the link for a PD requesting power, optionally classify the PD, supply power to the link if a PD is detected, monitor the power on the link, and disconnect power when it is no longer requested or required. A PD participates

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in the PD detection procedure by presenting a PoE detection signature defined by the IEEE 802.3af standard.

[0005] If the detection signature is valid, the PD has an option of presenting a classification signature to the PSE to indicate how much power it will draw when powered up. A PD may be classified as class 0 to class 4. A PD of class 1 requires that the PSE supplies at least 4.0W, a PD of class 2 requires that the PSE supplies at least 7.0W, and a PD of class 0, 3 or 4 requires at least 15.4W. Based on the determined class of the PD ₅ the PSE applies the required power to the PD.

[0006] A pass device, such as a MOSFET, may act as a switch between the PSE and the PD. During power-up and short-circuit conditions, power dissipation in the MOSFET may be much higher than power dissipation when nominal power is provided. To limit the power dissipation, a foldback mechanism is prescribed by the IEEE 802.3af standard. In particular, the standard defines that in a startup mode, for port voltages between 10V and 30V, the minimum requirement for an output current (Iin _n i _s h) is 6OmA. For port voltages above 30 V, the current Ii _n m _sh in a startup mode is required to be in the range from 40OmA to 45OmA. This 40OmA to 45OmA Ij _nmsh requirement applies for duration of the 50ms to 75ms T _LIM timer.

[0007] FIG. 1 shows a diagram that graphically illustrates the IEEE 802.3 af foldback requirements. In particular, the gray areas in FIG. 1 show combinations of PSE output voltages and output currents that are not allowed by the IEEE 802.3 af standard. The black line in FIG. 1 illustrates a possible foldback curve representing the output current of the PSE at a level between 40OmA and 45OmA for output voltages above 30V and gradually reduced for output voltages below 30V. The current limit foldback technique is used to limit dissipation power, and therefore, size and cost of the pass device.

[0008] However, for a high-power PSE capable of providing higher power to the PD than power mandated by the IEEE 802.3af specification, current limits should be higher than the 40OmA to 45OmA current prescribed by the IEEE 802.3af standard. Because higher currents cause higher MOSFET power dissipation, a larger pass device would be required. It would result in higher costs for the PSE manufacturer.

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[0009] Therefore, there is a need for a foldback mechanism that would reduce power dissipation of a pass device in a high-power PSE.

Summary of the Disclosure

[0010] The present disclosure offers a novel system and methodology for performing foldback. In accordance with one aspect of the disclosure, a system for supplying power to a load has a pass device for providing a connection to the load, a current limit circuit for preventing current supplied to the load from exceeding a current threshold, and a foldback circuit for modifying the current threshold in accordance with a prescribed condition. The foldback circuit is configured to vary the current threshold in accordance with an approximate safe operating area of the pass device.

[0011] For example, to comply with the IEEE 802.3af specification, the foldback circuit may reduce the current threshold when a voltage across the load is below a pre-set value.

[0012] The foldback circuit may monitor a voltage across the load, and/or a voltage across the pass device to correspondingly vary the current threshold so as to maintain a substantially constant level of DC power dissipated by the pass device. The maintained level of DC power may correspond to a maximum amount of dissipated power safely handled by the pass device.

[0013] In accordance with an embodiment of the disclosure, the foldback circuit may maintain the current threshold at a first level, such as the level prescribed by the IEEE

802.3af specification, when a voltage across the load is between a first voltage value and a second voltage value.

[0014] The current threshold may be reduced below the first level when the voltage across the load is below the first voltage value. For example, the foldback circuit may monitor the voltage across the load to reduce the current threshold below the first level.

[0015] The current threshold may be increased above the first level when the voltage across the load is above the second voltage value. The foldback circuit may monitor a voltage across the pass device to increase the current threshold above the first level.

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[0016] The foldback circuit may perform linear approximation of respective portions of the safe operating area when the current threshold is adjusted with respect to the first level. [0017] A foldback control circuit may control the foldback circuit so as to select variable values of the current threshold. In particular, the foldback control circuit may program the foldback circuit to operate within a specific application in order to maximize the utilization of a SOA for a particular pass device.

[0018] In accordance with another aspect of the disclosure, a system for supplying power to a powered device (PD) over a communication link, such as a Power over Ethernet (PoE) system, comprises a power supply device having an output port for providing power to the PD over the communications link. Power is supplied to the PD via a semiconductor device. A ^' current limit circuit prevents an output current of the power supply device from exceeding a current threshold, and a foldback circuit modifies the current threshold in accordance with a prescribed condition. The foldback circuit is configured to vary the current threshold so as to maintain a constant level of power dissipated by the semiconductor device. [0019] The foldback circuit may monitor a voltage at the output port and/or a voltage across the semiconductor device to modify the current threshold so as maintain a constant level of DC power dissipated by the semiconductor device. In particular, the foldback circuit may approximate the safe operating area of the semiconductor device.

[0020] In accordance with a method of the present disclosure, the following steps are carried .out to supply power to a load connected via a pass device;, -limiting current supplied to the load to a current threshold value, and

-varying the current threshold value to maintain a constant level of power dissipated by the pass device.

[0021] The current threshold value may be varied to approximate the safe operating area of the pass device.

[0022] Additional advantages and aspects of the disclosure will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the present disclosure are shown and described, simply by way of illustration of the best mode contemplated for practicing the present disclosure. As will be described, the disclosure is

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capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.

Brief Description of the Drawings

[0023] The following detailed description of the embodiments of the present disclosure can best be understood when read in conjunction with the following drawings, in which the features are not necessarily drawn to scale but rather are drawn as to best illustrate the pertinent features, wherein:

FIG. 1 is diagram illustrating the IEEE 802.3 affoldback requirements;

FIG. 2 is a diagram illustrating supplying power in PoE system;

FIG. 3 is a diagram illustrating a foldback mechanism of the present disclosure;

FIG. 4 is a diagram illustrating examples of safe operating area (SOA) of a pass device, and foldback curves for an IEEE 802.3 af-compliant PSE and a high-power PSE.

FIG. 5 is a diagram illustrating an exemplary foldback curve approximating the SOA.

FIG. 6 is a diagram illustrating an exemplary foldback curve providing the linear approximation of the SOA.

Detailed Disclosure of the Embodiments

[0024] The present disclosure will be made using the example of a PoE system. It will become apparent, however, that the concepts described herein are applicable to any system for supplying power to a load via a pass device.

[0025] FIG. 2 schematically illustrates voltages applied in a PoE system 10 between a PSE 12 and a PD 14. In particular, a PSE power supply may include positive terminal Vsupply ₊ and negative terminal Vsupply.. The PSE 12 may include a pass device 16, such as a power MOSFET, for connecting and disconnecting the PD 14 to and from the PSE 12. The gate of the power MOSFET 16 may be controlled to supply power from the PSE 12 to the PD 14.

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The voltage V _PD = Vsupply ₊ - Vport is applied across the PD 14, where Vport is a port voltage provided at the output port of the PSE 12. The power Ppass dissipated by the pass device is equal to Vpass x Iport, where Vpass = Vport — Vsupply. is the voltage applied across the pass device 16. When the voltage V _PD across the PD 14 decreases, the voltage Vpass across the pass device 16 increases.

[0026] When the PD 14 is being connected to the PSE 12, i.e. in a start-up mode, and during short-circuit conditions, power dissipation in the pass device 16 may be much higher than power dissipation when nominal power is provided. To limit the power dissipation, a foldback mechanism is prescribed by the IEEE 802.3af standard. In particular, the standard defines that for port voltages Vport between 10V and 30V, the minimum requirement for an output current (Iim _vs h) in the startup mode is 60mA. For port voltages Vport above 30 V, the minimum Ii _nrU sh requirement is in the range from 40OmA to 45OmA. The minimum Iinmsh requirement applies for duration T _L I _M set in the range between 50ms and 75ms. [0027] As shown in FIG. 3, the foldback mechanism may comprise a foldback circuit 102 that controls a current limit circuit 104 so as to control the port current Iport of the PSE 12 in _. accordance with foldback requirements. In particular, the current limit circuit 104 monitors the port current Iport and compares it with a current limit threshold to maintain the port . _. current Iport at or below the current limit threshold. '

[0028] The port current Iport may be monitored by determining sense voltage Vsense across sense resistor Rsense connected to the pass device 16, such as a MOSFET. The current limit circuit 104 may comprise an operational amplifier that compares the determined sense voltage. Vsense with a reference voltage Vref representing the current limit threshold to maintain the sense voltage at or below the Vref voltage. More specifically, the output of the operational amplifier may be connected to the gate of the MOSFET 16 to decrease gate drive voltage at the gate when the sense voltage Vsense increasing with an increase in- the port current approaches the reference voltage Vref. As a result, the resistance of the MOSFET 16 increases, reducing the port current Iport.

[0029] The current limit circuit 104 is controlled by the foldback circuit 102 that may change the voltage Vref so as to achieve a required value of Iport. The foldback circuit 102

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monitors the voltage V> _D = Vsupply ₊ - Vport applied across the PD 14, and/or the voltage Vpass = Vport — Vsupply. applied across the pass device 16. As described in more detail below, the foldback circuit 102 modifies the current limit threshold so as to limit power dissipated by the pass device 16 to a level corresponding to a safe operating area (SOA) of the pass device 16.

[0030] SOA of a pass device may be defined as the voltage and current conditions over which the pass device can be expected to operate without damage caused by the dissipation power, i.e. the SOA determines the amount of dissipation power the pass device can safely handle. The power Ppass dissipated by the pass device 16 is equal to Vpass x Iport. Decreasing the current limit threshold decreases the port current Iport flowing through the pass device 16. To limit the maximum power dissipation requirement in the pass device 16, the port current Iport should be decreased as the voltage Vpass across the pass device increases. This can lower the size and the cost of the pass device 16.

[0031] FIG. 4 illustrates an exemplary SOA of a pass device suitable for an IEEE 802.3af- compliant PSE. The SOA is represented by an area below the constant power curve defined by variable values of the port current Iport and the port voltage Vport. This power curve represents a maximum level of dissipation power Ppass that can be safely handled by the pass device 16. Also, FIG. 4 shows examples of foldback current limits for the IEEE 802.3af- compliant PSE, and for a high-power PSE that may provide higher amounts of power than the IEEE 802.3af standard requires.

[0032] In the illustrated example, the foldback current limit for the high-power PSE is doubled compared to the IEEE 802.3 af-compliant PSE, and allowed foldback voltage level remains the same. As a result, the pass device of the high-power PSE would be required to dissipate twice the power level of the IEEE 802.3 af-compliant pass device. This power dissipation would he outside the illustrated SOA. Therefore, a larger pass device would be required.

[0033] To avoid using a larger pass device, the foldback circuit 102 of the present disclosure implements a foldback scheme that allows the PSE to deliver higher power without violating the SOA of a pass device suitable for the IEEE 802.3 af-compliant PSE. As illustrated in

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FIG. 5, the foldback circuit 102 may define the current limit threshold values so as to approximate the SOA of the pass device 16. In particular, the foldback circuit 102 may monitor the voltage Vpo across the PD 14, and/or the voltage Vpass across the pass device 16 to define the current limit threshold so as to maintain a constant level of DC power dissipated by the pass device 16. The maintained DC power lower may be set at a level that can be safely handled by the pass device 16, i.e. at or below the constant power curve corresponding to the SOA of the pass device 16.

[0034] To implement this foldback scheme, the foldback circuit 102 may determine the reference voltage Vref as a function of the voltage Vpo and/or the voltage Vpass to provide a constant level of DC power dissipation within the SOA of the pass device 16. The foldback circuit 102 may include logic circuits, such as multipliers, and other components for determining the reference voltage Vref. Alternatively, the foldback circuit 102 may be implemented using a general purpose digital signal processor and appropriate programming. [0035] The foldback mechanism may further comprise a control logic circuit 106 for controlling the foldback circuit 102. In particular, the control logic circuit 106 may program the current limit curve produced by the foldback circuit 102 within a specific application to allow the system designer to maximize the utilization of a SOA for a particular pass device. The control logic circuit 106 may program the slopes, intermediate and final values of the current limit curve produced by the foldback circuit 102.

[0036] FIG. 6 illustrates another foldback scheme using a foldback current limit that provides a linear approximation of the SOA. To implement this foldback scheme, the foldback circuit 102 may maintain the current limit threshold at a 425 mA level prescribed by the EEEE 802.3 af specification when the Vport voltage varies between values Vl and V2 programmable by the control logic circuit 106 to approximate a SOA of a particular pass device 16. When the Vport voltage is below Vl, the current limit threshold may be linearly reduced so as to approximate the respective portion of the SOA. When the Vport voltage is above V2, the current limit threshold may be linearly increased to approximate the respective portion of the SOA. The current limit threshold may be increased until it reaches a level sufficient to enable the PSE 12 to deliver a required amount of power to the PD 14. For

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example, the upper portion of the current limit threshold may be set at a 850 mA level corresponding to the example illustrated in FIG. 4.

[0037] To implement the foldback scheme illustrated in FIG. 6, the foldback circuit 102 may monitor the' voltage V _PD across the PD 14, and/or the voltage Vpass across the pass device 16 to determine values of the reference voltage Vref defining the current limit threshold. For example, the VPD voltage may be monitored to define a lower portion of the threshold curve, and the Vpass voltage may be monitored to define an upper portion of the threshold curve.

The Vl and V2 values and the slopes of the current threshold lines may be programmed by the control logic circuit 106 to maximize utilization of the SOA.

[0038] The foregoing description illustrates and describes aspects of the present invention.

Additionally, the disclosure shows and describes only preferred embodiments, but as aforementioned, it is to be understood that the invention is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings, and/or the skill or knowledge of the relevant art.

[0039] The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments and with the various modifications required by the particular applications or uses of the invention.

[0040] Accordingly, the description is not intended to limit the invention to the form disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments.

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