Background

[0001] Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

Brief Description of the Drawings

[0002] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings.

[0003] FIGS. 1A-1C are cross-sectional views of an example quantum dot device including a quantum dot gate and a vertical transistor, in accordance with various embodiments.

[0004] FIGS. 2A-2X illustrate various example stages in the manufacture of the quantum dot device of FIGS. 1A-1C, in accordance with various embodiments.

[0005] FIGS. 3A-3D are cross-sectional views of an example quantum dot device including an array of quantum dot gates and an array of vertical transistors, in accordance with various embodiments.

[0006] FIGS. 4A-4K illustrate various example stages in the manufacture of the quantum dot device of FIGS. 3A-3D, in accordance with various embodiments.

[0007] FIGS. 5A-5E are cross-sectional views of an example quantum dot device including an array of quantum dot gates and an array of vertical transistors, in accordance with various embodiments.

[0008] FIGS. 6A-6H illustrate various example stages in the manufacture of the quantum dot device of FIGS. 5A-5E, in accordance with various embodiments.

[0009] FIGS. 7A-7D are cross-sectional views of an example quantum dot device including an array of quantum dot gates and an array of vertical transistors, in accordance with various embodiments.

[0010] FIGS. 8A-8C illustrate various embodiments of a quantum well stack that may be included in a quantum dot device, in accordance with various embodiments.

[0011] FIG. 9 is a perspective view of a portion of a quantum dot device including vertical transistors, in accordance with various embodiments.

[0012] FIG. 10 is a side cross-sectional view of an example quantum dot device including a magnet line, in accordance with various embodiments. [0013] FIG. 11 is a flow diagram of an illustrative method of operating a quantum dot device, in accordance with various embodiments.

[0014] FIG. 12 shows top view of a wafer and dies that may include any of the quantum dot devices disclosed herein.

[0015] FIG. 13 is a cross-sectional side view of a device assembly that may include any of the dot devices disclosed herein.

[0016] FIG. 14 is a block diagram of an example computing device that may include any of the quantum dot devices disclosed herein, in accordance with various embodiments.

Detailed Description

[0017] Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of transistors above the array of quantum dot gate electrodes, wherein the array of quantum dot gate electrodes and the array of transistors are each arranged in a grid.

[0018] The quantum dot devices disclosed herein may enable the formation of quantum dots to serve as quantum bits ("qubits") in a quantum computing device, as well as the control of these quantum dots to perform quantum logic operations. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein provide strong spatial localization of the quantum dots (and therefore good control over quantum dot interactions and manipulation), good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

[0019] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0020] Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment.

Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. Terms like "first," "second," "third," etc. do not imply a particular ordering, unless otherwise specified. As used herein, a "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide.

[0021] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C). For ease of discussion, all the lettered sub-figures associated with a particular numbered figure may be referred to by the number of that figure; for example, FIGS. 1A-1C may be referred to as "FIG. 1," FIGS. 2A-2X may be referred to as "FIG. 2," etc.

[0022] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The disclosure may use the singular term "layer," but the term "layer" should be understood to refer to assemblies that may include multiple different material layers. The accompanying drawings are not necessarily drawn to scale.

[0023] FIGS. 1A-1C are cross-sectional views of an example quantum dot device 150 including a vertical transistor 100, in accordance with various embodiments. In particular, FIG. 1A is a "side" cross-sectional view (through the section A-A of FIGS. IB and 1C), FIG. IB is a "top" cross-sectional view (through the section B-B of FIG. 1A), and FIG. 1C is a "top" cross-sectional view (through the section C-C of FIG. 1A). The vertical transistor 100 may include a bottom source/drain (S/D) contact 102, a top S/D contact 104, and a channel 103 disposed between the S/D contacts 102 and 104. A gate dielectric 108 may laterally surround the channel 103, and a gate electrode 106 may laterally surround the gate dielectric 108 such that the gate dielectric 108 is disposed between the gate electrode 106 and the channel 103. The gate electrode 106 may control current flow in the channel 103 between the S/D contact 102 and the S/D contact 104, and the conductive pathways 163 and 165 to the S/D contacts 102 and 104, respectively, may route electrical signals to/from the S/D contacts 102 and 104.

[0024] The materials of the gate dielectric 108 and the gate electrode 106 may take any suitable form. For example, the gate electrode 106 may include at least one p-type work function metal or n- type work function metal, depending on whether the vertical transistor 100 is to be a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. For a PMOS transistor, metals that may be used for the gate electrode 106 of the vertical transistor 100 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode of the vertical transistor 100 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode 106 of the vertical transistor 100 may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as to act as a barrier layer.

[0025] The gate dielectric 108 of the vertical transistor 100 may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric 108 of the vertical transistor 100 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of materials that may be used in the gate dielectric 108 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric 108 to improve the quality of the gate dielectric 108.

[0026] In some embodiments, the channel 103 may be formed of a thin film material. Some such materials may be deposited at relatively low temperatures, which makes them depositable within the thermal budgets imposed on back-end fabrication to avoid damaging the front-end components. In some embodiments, the channel 103 may be formed of an amorphous, polycrystalline, or crystalline semiconductor, or an amorphous, polycrystalline, or crystalline semiconducting oxide. In some embodiments, the channel 103 may be formed of an amorphous, polycrystalline, or crystalline group lll-V material; amorphous, polycrystalline, or crystalline silicon; amorphous, polycrystalline, or crystalline germanium; amorphous, polycrystalline, or crystalline silicon germanium; amorphous, polycrystalline, or crystalline gallium arsenide; amorphous, polycrystalline, or crystalline indium antimonide; amorphous, polycrystalline, or crystalline indium gallium arsenide; amorphous, polycrystalline, or crystalline gallium antimonide; amorphous, polycrystalline, or crystalline tin oxide; amorphous, polycrystalline, or crystalline indium gallium oxide (IGO); or amorphous, polycrystalline, or crystalline indium gallium zinc oxide (IGZO). [0027] In FIG. 1, the S/D contact 102 is in contact with a conductive pathway 163 that may route electrical signals to and/or from the S/D contact 102. In FIG. 1, the conductive pathway 163 is illustrated as including a conductive via 112 and a conductive line 114. In some embodiments, the conductive line 114 of the conductive pathway 163 may be a bit line, as discussed below. The arrangement of conductive lines and vias in the conductive pathway 163 to the S/D contact 102 in FIG. 1 is simply illustrative, and any suitable interconnect arrangement may be used. As discussed further below, the conductive pathway 163 may contact a quantum dot gate electrode 212, conductively coupling the S/D contact 102 and the quantum dot gate electrode 212.

[0028] The S/D contact 104 of FIG. 1 is in contact with a conductive pathway 165 that may route electrical signals to and/or from the S/D contact 104. In FIG. 1, the conductive pathway 165 is illustrated as including a conductive via 112 and a conductive line 114, but this is simply illustrative, and any suitable interconnect arrangement may be used. For example, in some embodiments, the conductive line 114 of the conductive pathway 165 may be a bit line, as discussed below. In some embodiments, the conductive line 114 of the conductive pathway 165 may directly contact the S/D contact 104, without an intervening conductive via 112.

[0029] A number of different conductive materials may be used for the S/D contacts 102 and 104. In some embodiments, the S/D contacts 102 and/or 104 may include a metal, such as copper. In some embodiments, the S/D contacts 102 and/or 104 may include a doped semiconductor, such as silicon or another semiconductor doped with an n-type dopant or a p-type dopant. For example, the S/D contacts 102 and/or 104 may be formed using either an implantation/diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into a material to form the S/D contacts 102 and/or 104. An annealing process that activates the dopants and causes them to diffuse farther into the material may follow the ion implantation process. In the latter process, an epitaxial deposition process may provide material that is used to fabricate the S/D contacts 102 and/or 104. In some implementations, the S/D contacts 102 and/or 104 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D contacts 102 and/or 104 may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D contacts 102 and/or 104. In some embodiments, an etch process may be performed before the epitaxial deposition to create recesses in which the material for the S/D contacts 102 and/or 104 is deposited. Metals may provide higher conductivity to the S/D contacts 102 and/or 104, while doped semiconductors may be easier to pattern during fabrication.

[0030] The gate electrode 106 of FIG. 1 is in contact with a conductive pathway 167 that may route electrical signals to and/or from the gate electrode 106. In FIG. 1, the conductive pathway 167 is illustrated as including a conductive via 112 and a conductive line 114, but this is simply illustrative, and any suitable interconnect arrangement may be used. For example, in some embodiments, the gate electrode 106 itself may be part of a word line for a memory cell including the vertical transistor 100, as discussed below, and the conductive via 112 may serve as a conductive contact to this word line for multiple vertical transistors 100. The conductive lines 114 may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 202 of the quantum dot device 150. For example, the conductive lines 114 may route electrical signals in a direction in and out of the page, or left and right in the page, from the perspective of FIG. 1A. The conductive vias 112 may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 202 of the quantum dot device 150. The conductive vias 112 and lines 114 included in a quantum dot device 150 may include any suitable materials, such as copper, tungsten (deposited, e.g., by chemical vapor deposition (CVD)), or a superconductor (e.g., aluminum, tin, titanium nitride, niobium titanium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium).

[0031] An insulating material 124 may be disposed around the vertical transistor 100 and the electrical interconnects of FIG. 1, as shown. In some embodiments, some or all the different layers in the quantum dot device 150 may include insulating materials 124 with different material compositions; in other embodiments, the composition of the insulating material 124 may be the same between different layers. The insulating material 124 may be a dielectric material, such as silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride. In some embodiments, the insulating material 124 may be any suitable interlayer dielectric (ILD) material.

[0032] The components of the vertical transistors 100 disclosed herein may have dimensions of any suitable values. For example, in some embodiments, the S/D contact 102 may have a thickness 185 between 100 nanometers and 300 nanometers (e.g., 200 nanometers). In some embodiments, a thickness 183 of the channel 103, the gate dielectric 108, and the gate electrode 106 may be approximately the same, and/or each may be between 10 nanometers and 100 nanometers (e.g., between 40 nanometers and 50 nanometers). In some embodiments, the S/D contact 104 may have a thickness 181 between 10 nanometers and 300 nanometers (e.g., 200 nanometers). In some embodiments, the width 191 of the S/D contact 102, the channel 103, and the S/D contact 104 may be approximately the same, and/or each may be between 10 nanometers and 15 nanometers. In some embodiments, the width 189 of the gate dielectric 108 may be between 2 nanometers and 3 nanometers. In some embodiments, the width 187 of the gate electrode 106 may be between 10 nanometers and 20 nanometers. In some embodiments, the total lateral width of the vertical transistor 100 (i.e., the sum of the width 191, twice the width 189, and twice the width 187) may be between 20 nanometers and 100 nanometers (e.g., between 30 nanometers and 70 nanometers, or approximately 50 nanometers). In some embodiments, the width of the S/D contacts 102 and 104 may be different from (e.g., larger than) the width of the channel 108; in some such embodiments, the width of the S/D contacts 102 and 104 may each be between 20 nanometers and 100 nanometers (e.g., between 30 nanometers and 70 nanometers, or approximately 50 nanometers), and/or may be less than the total lateral width of the vertical transistor 100. In some embodiments including an array of vertical transistors 100 and an array of quantum dot gates 208 (e.g., as discussed below with reference to FIGS, 3, 5, 7, and 9), the pitch of the transistors 100 may be equal to the pitch of the quantum dot gates 208.

[0033] The conductive pathway 163 of FIG. 1 may be in conductive contact with a quantum dot gate 208. In the embodiment illustrated in FIG. 1, the vertical transistor 100 is shown as located in the "next" layer above the quantum dot gate 208, but this is simply illustrative; a vertical transistor 100 and its associated quantum dot gate 208 may be spaced apart by any desired number and arrangement of interconnect structures (e.g., conductive vias and/or lines).

[0034] The quantum dot device 150 may further include a substrate 202, a quantum well stack 246, and one or more quantum dot gates 208 above the quantum well stack 246. The quantum well stack 246 may include one or more quantum well layers; examples of quantum well stacks 246 and quantum well layers are discussed in detail below with reference to FIG. 8. A quantum well layer included in a quantum well stack 246 may be arranged normal to the z-direction, and may provide a layer in which a two-dimensional electron gas (2DEG) may form to enable the generation of a quantum dot during operation of the quantum dot device 150, as discussed in further detail below. A quantum well layer itself may provide a geometric constraint on the z-location of quantum dots in the quantum well stack 246. To control the x-location and the y-location of quantum dots, voltages may be applied to quantum dot gates 208 disposed above the quantum well stack 246 to adjust the energy profile along the quantum well stack 246 in the x-direction and the y-direction and thereby constrain the x-location and y-location of quantum dots within quantum wells (discussed in detail below with reference to the quantum dot gates 208).

[0035] One or more quantum dot gates 208 may be disposed above the quantum well stack 246. FIG. 1 illustrates a single quantum dot gate 208, while FIGS. 3, 5, and 7 illustrate quantum dot devices 150 including multiple quantum dot gates 208. The particular number of and arrangement of quantum dot gates 208 in the accompanying drawings is simply illustrative, and any suitable number and arrangement of gates may be used. For example, three or more quantum dot gates 208 may be arranged in any desired arrangement (e.g., as vertices of triangles or other polygons, in a rectangular or other array, in an irregular arrangement on the quantum well stack 246, etc.). In some embodiments, a quantum dot device 150 may include multiple quantum dot gates 208 that include at least one pair of quantum dot gates 208 spaced apart from each other in a first dimension (e.g., spaced apart from each other in the x-dimension), and at least one pair of quantum dot gates 208 spaced apart from each other in a second dimension perpendicular to the first dimension (e.g., spaced apart from each other in the y-dimension). A two-dimensional regular array of spaced-apart quantum dot gates 208 is one example of such an arrangement (e.g., as illustrated in FIGS. 3, 5, and 7), but many others exist (e.g., an irregular array or other distribution). These pairs may share a quantum dot gate 208; for example, three quantum dot gates 208 may satisfy this description if arranged accordingly. In the embodiment illustrated in FIGS. 3, 5, and 7, different ones of the quantum dot gates 208 are spaced apart by intervening portions of the insulating material 210; in other embodiments, other materials or structures may be disposed between adjacent quantum dot gates 208. The insulating material 210 may have any suitable material composition. For example, in some embodiments, the insulating material 210 may include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride. In some embodiments, the insulating material 210 may be a spacer material. The insulating material 210 may be patterned in any suitable way to define the location and shape of the quantum dot gates 208.

[0036] Each of the quantum dot gates 208 may include a quantum dot gate dielectric 214. Separate portions of the quantum dot gate dielectric 214 may be provided for each of the quantum dot gates 208, and in some embodiments, the quantum dot gate dielectric 214 may extend at least partially up the side walls of the proximate insulating material 210. In such embodiments, the quantum dot gate electrode 212 may extend between the portions of the associated quantum dot gate dielectric 214 on the side walls of the proximate insulating material 210, and thus may have a U-shape in cross section (as illustrated in FIG. 1A). In some embodiments, the quantum dot gate dielectric 214 may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the quantum well stack 246 and the quantum dot gate electrode 212). The quantum dot gate dielectric 214 may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the quantum dot gate dielectric 214 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of materials that may be used in the quantum dot gate dielectric 214 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the quantum dot gate dielectric 214 to improve the quality of the quantum dot gate dielectric 214. The quantum dot gate dielectric 214 may be a same material as the gate dielectric 108, or a different material.

[0037] Each of the quantum dot gates 208 may include a quantum dot gate electrode 212. In some embodiments, a hardmask 218 may be disposed above the quantum dot gate electrode 212. The hardmask 218 may be formed of silicon nitride, silicon carbide, or another suitable material. The quantum dot gate electrode 212 may be disposed between the hardmask 218 and the quantum dot gate dielectric 214, and the quantum dot gate dielectric 214 may be disposed between the quantum dot gate electrode 212 and the quantum well stack 246. In some embodiments, the quantum dot gate electrode 212 may be a superconductor, such as aluminum, tin, titanium nitride, niobium titanium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium. In some embodiments, the hardmask 218 may not be present in the quantum dot device 150 (e.g., a hardmask like the hardmask 218 may be removed during processing, as discussed below).

[0038] The quantum dot device 150 may include accumulation regions 240 that may serve as a reservoir of charge carriers for the quantum dot device 150. In some embodiments, the

accumulation regions 240 may be separated by a thin insulating barrier from the quantum well layer of the quantum well stack 246. For example, an n-type accumulation region 240 may supply electrons for electron-type quantum dots, and a p-type accumulation region 240 may supply holes for hole-type quantum dots. In some embodiments, an interface material 241 may be disposed at a surface of an accumulation region 240. The interface material 241 may facilitate electrical coupling between a conductive contact (e.g., a conductive via 112, as shown in FIG. 1) and the accumulation region 240. The interface material 241 may be any suitable metal-semiconductor ohmic contact material; for example, in embodiments in which the accumulation region 240 includes silicon, the interface material 241 may include nickel silicide, aluminum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tungsten silicide, or platinum silicide. In some embodiments, the interface material 241 may be a non-silicide compound, such as titanium nitride. In some embodiments, the interface material 241 may be a metal (e.g., aluminum, tungsten, or indium).

[0039] Conductive vias and lines may contact the quantum dot gates 208, and the accumulation regions 240, to enable electrical connection to the quantum dot gates 208 and the accumulation regions 240 to be made in desired locations. As shown in FIG. 1, the quantum dot gates 208 may extend away from the quantum well stack 246, and conductive vias 112 may extend through the insulating material 124 to contact the quantum dot gate electrode 212 of the quantum dot gate 208 (thereby electrically coupling the S/D contact 102 with the quantum dot gate electrode 212). The conductive vias 112 may extend through the hardmask 218 to contact the quantum dot gate electrode 212. Conductive vias 112 may contact the interface material 241 and may thereby make electrical contact with the accumulation regions 240.

[0040] The dimensions of the quantum well stack 246, the insulating material 210, and the quantum dot gates 208 may take any suitable values. For example, in some embodiments, the z- height 266 of the insulating material 210 and the quantum dot gate electrode 212 may be between 40 nanometers and 75 nanometers (e.g., approximately 50 nanometers). In some embodiments, the distance 268 between adjacent quantum dot gates 208 (see, e.g., FIG. 3) may be less than 150 nanometers (e.g., between 20 nanometers and 150 nanometers, between 20 nanometers and 40 nanometers, approximately 30 nanometers, or approximately 50 nanometers). In some

embodiments, the length 270 of the quantum dot gates 208 may be between 40 nanometers and 60 nanometers (e.g., 50 nanometers). In some embodiments, the z-height 264 of the quantum well stack 246 may be between 200 nanometers and 400 nanometers (e.g., between 250 nanometers and 350 nanometers, or approximately 300 nanometers).

[0041] During operation of the quantum dot device 150, voltages may be applied to the quantum dot gate 208, under the control of the vertical transistor 100, to adjust the potential energy in the quantum well layer(s) in the quantum well stack 246 to create quantum wells of varying depths in which quantum dots may form. The portions of insulating material 210 disposed between adjacent quantum dot gates 208 may themselves provide "passive" barriers between quantum wells under the quantum dot gates 208 in the quantum well stack 246, and the voltages applied to different ones of the quantum dot gates 208 may adjust the potential energy under the quantum dot gates 208 in the quantum well stack 246; decreasing the potential energy may form quantum wells, while increasing the potential energy may form quantum barriers.

[0042] The quantum dot devices 150 disclosed herein may be used to form electron-type or hole- type quantum dots. Note that the polarity of the voltages applied to the quantum dot gates 208 (mediated by the vertical transistors 100) to form quantum wells/barriers depend on the charge carriers used in the quantum dot device 150. In embodiments in which the charge carriers are electrons (and thus the quantum dots are electron-type quantum dots), amply negative voltages applied to a quantum dot gate 208 may increase the potential barrier under the quantum dot gate 208, and amply positive voltages applied to a quantum dot gate 208 may decrease the potential barrier under the quantum dot gate 208 (thereby forming a potential well in the quantum well layer(s) in which an electron-type quantum dot may form). In embodiments in which the charge carriers are holes (and thus the quantum dots are hole-type quantum dots), amply positive voltages applied to a quantum dot gate 208 may increase the potential barrier under the quantum dot gate 208, and amply negative voltages applied to a quantum dot gate 208 may decrease the potential barrier under the quantum dot gate 208 (thereby forming a potential well in the associated quantum well layer(s) in which a hole-type quantum dot may form).

[0043] Voltages may be applied to each of the quantum dot gates 208 separately (under the control of the associated vertical transistor 100) to adjust the potential energy in the quantum well layer under the quantum dot gates 208, and thereby control the formation of quantum dots in the quantum well stack 246 under each of the quantum dot gates 208. Additionally, the relative potential energy profiles under different ones of the quantum dot gates 208 allow the quantum dot device 150 to tune the potential interaction between quantum dots under different quantum dot gates 208. For example, if two quantum dots (e.g., one quantum dot under a quantum dot gate 208 and another quantum dot under another quantum dot gate 208) are separated by only a short potential barrier, the two quantum dots may interact more strongly than if they were separated by a taller potential barrier. Since the depth of the potential wells/height of the potential barriers under each quantum dot gate 208 may be adjusted by adjusting the voltages on the respective quantum dot gates 208 and neighboring gates, the differences in potential between various quantum dot gates 208 may be adjusted, and thus the interaction tuned. In some applications, the quantum dot gates 208 may be used as plunger gates to enable the formation of quantum dots under the quantum dot gates 208.

[0044] During operation, a bias voltage may be applied to the accumulation regions 240 (e.g., via the conductive via 112 and the interface material 241) to cause current to flow through the accumulation regions 240. When the accumulation regions 240 are doped with an n-type material, this voltage may be positive; when the accumulation regions 240 are doped with a p-type material, this voltage may be negative. The magnitude of this bias voltage may take any suitable value (e.g., between 0.25 volts and 2 volts). In some embodiments, the bias voltage applied to an accumulation region 240 may not be regulated by a vertical transistor 100.

[0045] The quantum dot devices 150 disclosed herein may be formed using any suitable technique. For example, FIGS. 2A-2X illustrate various example stages in the manufacture of the quantum dot device 150 of FIG. 1, in accordance with various embodiments.

[0046] FIG. 2A illustrates a cross-sectional view of an assembly including a substrate 202 and a quantum well stack 246 on the substrate 202. The substrate 202 may include any suitable semiconductor material or materials, or any other suitable structure on which to perform the subsequent operations. In some embodiments, the substrate 202 may include a semiconductor material. For example, the substrate 202 may be a silicon wafer, a germanium wafer, a wafer including a group lll-V material, etc. The quantum well stack 246 may include at least one quantum well layer. As discussed above, a 2DEG may form in the quantum well layer during operation of the quantum dot device 150. Various embodiments of the quantum well stack 246 are discussed below with reference to FIG. 8.

[0047] FIG. 2B is a cross-sectional view of an assembly subsequent to providing an insulating material 210 on the quantum well stack 246 of the assembly of FIG. 2A. The insulating material 210 may take any of the forms disclosed herein, and may be deposited using any suitable technique.

[0048] FIG. 2C is a cross-sectional view of an assembly subsequent to patterning the insulating material 210 of the assembly of FIG. 2B. The patterning of the insulating material 210 may include forming recesses in the insulating material 210, exposing the quantum well stack 246, in which the quantum dot gate 208 will be formed (as discussed below). Any suitable techniques may be used to pattern the insulating material 210, such as a photobucket technique or other technique.

[0049] FIG. 2D is a cross-sectional view of an assembly subsequent to providing a quantum dot gate dielectric 214 on the assembly of FIG. 2C. In particular, the quantum dot gate dielectric 214 may be disposed on the quantum well stack 246 between portions of the insulating material 210. In some embodiments, the quantum dot gate dielectric 214 may be formed by atomic layer deposition (ALD) and, as illustrated in FIG. 2D, may cover the exposed quantum well stack 246 and extend onto the adjacent insulating material 210.

[0050] FIG. 2E is a cross-sectional view of an assembly subsequent to providing material for the quantum dot gate electrode 212 on the assembly of FIG. 2D. The material of the quantum dot gate electrode 212 may fill the recesses in the insulating material 210 (between the quantum dot gate dielectric 214-1 disposed on adjacent side walls of the insulating material 210-1), and may extend over the insulating material 210. The material of the quantum dot gate electrode 212 may be provided using any suitable technique.

[0051] FIG. 2F is a cross-sectional view of an assembly subsequent to planarizing the assembly of FIG. 2E to remove the material of the quantum dot gate electrode 212 and the quantum dot gate dielectric 214 above the insulating material 210. In some embodiments, the assembly may be planarized using a chemical mechanical polishing (CMP) technique.

[0052] FIG. 2G is a cross-sectional view of an assembly subsequent to providing a hardmask 218 on the planarized surface of the assembly of FIG. 2F. The hardmask 218 may be formed of an electrically insulating material, such as silicon nitride or carbon-doped nitride, or any of the other materials discussed above.

[0053] FIG. 2H is a cross-sectional view of an assembly subsequent to patterning the hardmask 218 and the insulating material 210 of the assembly of FIG. 2G. The hardmask 218 and the insulating material 210 may be patterned by applying a resist, patterning the resist using lithography, and then etching the hardmask (using dry etching or any appropriate technique). The patterned hardmask 218 may remain on top of the insulating material 210 and quantum dot gate 208, as shown, or it may be removed.

[0054] FIG. 21 is a cross-sectional view of an assembly subsequent to doping the quantum well stack 246 of the assembly of FIG. 2H to form accumulation regions 240 in the quantum well stack 246 adjacent to the insulating material 210. The accumulation regions 240 may be in conductive contact with one or more quantum well layers. In some embodiments, the accumulation regions 240 may be a single accumulation region 240 that extends around a periphery of the quantum dot device 150 (e.g., around an array of quantum dot gates 208, as illustrated in FIGS. 3, 5, and 7). The type of dopant used to form the accumulation regions 240 may depend on the type of quantum dot desired, as discussed above. In some embodiments, the doping may be performed by ion implantation. For example, when a quantum dot is to be an electron-type quantum dot, the accumulation regions 240 may be formed by ion implantation of phosphorous, arsenic, or another n-type material. When a quantum dot is to be a hole-type quantum dot, the accumulation regions 240 may be formed by ion implantation of boron or another p-type material. An annealing process that activates the dopants and causes them to diffuse farther into the quantum well stack 246 may follow the ion implantation process. The depth of the accumulation regions 240 may take any suitable value; for example, in some embodiments, the accumulation regions 240 may each have a depth between 500 Angstroms and 1000 Angstroms. The outer portions of the insulating material 210 may provide a doping boundary, limiting diffusion of the dopant from the accumulation regions 240 into the area under the quantum dot gate 208. In some embodiments, the accumulation regions 240 may extend under the adjacent insulating material 210. In some embodiments, the accumulation regions 240 may extend past the adjacent insulating material 210, or may terminate under the adjacent insulating material 210 and not reach the boundary between the adjacent insulating material 210-2 and the proximate quantum dot gate electrode 212. The doping concentration of the accumulation regions 240 may, in some embodiments, be between 10 ¹⁷ /cm ³ and 10 ²⁰ /cm ³ .

[0055] FIG. 2J is a cross-sectional side view of an assembly subsequent to providing a layer of nickel or other material 243 over the assembly of FIG. 21. The nickel or other material 243 may be deposited using any suitable technique (e.g., a plating technique, CVD, or ALD). [0056] FIG. 2K is a cross-sectional side view of an assembly subsequent to annealing the assembly of FIG. 2J to cause the material 243 to interact with the accumulation regions 240 to form the interface material 241, then removing the unreacted material 243. When the accumulation regions 240 include silicon and the material 243 includes nickel, for example, the interface material 241 may be nickel silicide. Materials other than nickel may be deposited in the operations discussed above with reference to FIG. 2J to form other interface materials 241, including titanium, aluminum, molybdenum, cobalt, tungsten, or platinum, for example.

[0057] FIG. 2L is a cross-sectional view of an assembly subsequent to providing an insulating material 124 on the assembly of FIG. 2K. The insulating material 124 may take any of the forms discussed above. For example, the insulating material 124 may be a dielectric material, such as silicon oxide. The insulating material 124 may be provided using any suitable technique, such as spin coating, CVD, or plasma-enhanced CVD (PECVD). In some embodiments, the insulating material 124 may be polished back after deposition, and before further processing.

[0058] FIG. 2M is a side cross-sectional view of an assembly subsequent to forming an interconnect structure including the conductive pathway 163 on the assembly of FIG. 2L so that the conductive pathway 163 is in conductive contact with the quantum dot gate electrode 212, as well as forming a conductive via 112 and conductive line 114 in contact with the interface material 241. Insulating material 124 may be disposed around the conductive pathway 163 in the assembly of FIG. 2M. Any suitable fabrication techniques may be used to form the assembly of FIG. 2M (e.g., subtractive, additive, Damascene, dual Damascene, etc.).

[0059] FIG. 2N is a side cross-sectional view of an assembly subsequent to providing material for the S/D contact 102, material for the channel 103, and material for the S/D contact 104 on the assembly of FIG. 2M. FIGS. 2N-2X omit the layers of the assembly below and including the quantum dot gate 208 for ease of illustration. The techniques used to provide the material for the S/D contact 102 and the S/D contact 104 may depend on the particular materials, and may include ALD, physical vapor deposition (PVD), or CVD. In embodiments in which the S/D contacts 102 and 104 include a dopant, a material may be initially deposited and then doped with the dopant using any suitable technique. As noted above, in some embodiments, the material for the channel 103 may be deposited using a thin film deposition technique (e.g., sputtering, evaporation, molecular beam epitaxy (MBE), CVD, or ALD).

[0060] FIG. 20 is a side cross-sectional view of an assembly subsequent to providing a layer of mask material 201 on the assembly of FIG. 2N and patterning the mask material 201. A portion of the material for the S/D contact 104 may be exposed by the patterning of the mask material 201, and the pattern in the mask material 201 may correspond to a desired pattern for the S/D contact 102, channel 103, and S/D contact 104, as known in the art and as discussed below. In some embodiments, the mask material 201 may be a photoresist that may be removed in subsequent operations. In some embodiments, the mask material 201 may be a hardmask that may be removed or may remain as part of the quantum dot device 150 (not shown in the drawings for clarity of illustration).

[0061] FIG. 2P is a side cross-sectional view of an assembly subsequent to patterning the material for the S/D contact 104, the material for the channel 103, and the material for the S/D contact 102 of the assembly of FIG. 20 to form the S/D contact 104, the channel 103, and the S/D contact 102. In FIG. 2P, the S/D contact 102 is in conductive contact with the quantum dot gate electrode 212. FIG. 2Q is a top cross-sectional view of the assembly of FIG. 2P (through the section B-B of FIG. 2P) such that the view of FIG. 2P is taken through the section A-A of FIG. 2Q. The assembly of FIG. 2P may thus include a pillar 203 extending from the conductive line 114 of the conductive pathway 163, wherein the pillar 203 includes the S/D contact 102, the channel 103, and the S/D contact 104. As used herein, "patterning" may refer to forming a pattern in one or more materials using any suitable techniques (e.g., applying a resist, patterning the resist using lithography, and then etching the one or more material using dry etching, wet etching, or any appropriate technique). In some embodiments, the formation of the pillar 203 may be performed in a single set of etch operations, while in other embodiments, the pillar 203 may be formed by etching a ridge into the assembly of FIG. 20 (e.g., ridges that extend in and out of the plane of the drawing), then performing another set of etch operations to form the ridge into a pillar 203 (e.g., by etching trenches in planes parallel to the plane of the drawing). As discussed below, multiple pillars 203 may be formed using such techniques, although only a single pillar 203 is shown in FIGS. 2P and 2Q for clarity of illustration.

[0062] FIG. 2 is a side cross-sectional view of an assembly subsequent to providing insulating material 124 around the pillar 203 of the assembly of FIGS. 2P and 2Q. In some embodiments, the insulating material 124 may initially be deposited to extend over the pillar 203, then the insulating material 124 may be recessed back so that the insulating material 124 extends up the pillar 203 to the height of the S/D contact 102. Any suitable technique may be used to provide the insulating material 124, such as spin coating, CVD, or PECVD.

[0063] FIG. 2S is a side cross-sectional view of an assembly subsequent to conformally depositing material for the gate dielectric 108 on the assembly of FIG. 2R. The material for the gate dielectric 108 may be deposited on the exposed portions of the pillar 203 (including the side faces of the channel 103) and on the exposed surface of the insulating material 124. As noted elsewhere herein, the material for the gate dielectric 108 may take the form of any of the gate dielectric materials discussed herein. For example, the gate dielectric 108 may be a multilayer gate dielectric including multiple different materials. In some embodiments, the gate dielectric 108 may be deposited using ALD.

[0064] FIG. 2T is a side cross-sectional view of an assembly subsequent to performing a directional (or "anisotropic") etch on the material for the gate dielectric 108 in the assembly of FIG. 2S to remove some of the material for the gate dielectric 108 while leaving the gate dielectric 108 on the exposed side faces of the channel 103. In this manner, the gate dielectric 108 may surround the channel 103 in the assembly of FIG. 2T. In some embodiments, the directional etch may be a dry etch.

[0065] FIG. 2U is a side cross-sectional view of an assembly subsequent to depositing material for the gate electrode 106 of the assembly of FIG. 2T. Any suitable technique may be used to deposit the material for the gate electrode 106, such as sputtering, evaporation, ALD, or CVD techniques. As noted elsewhere herein, the material for the gate electrode 106 may take the form of any of the gate electrode materials discussed herein. In some embodiments, the material for the gate electrode 106 may initially be deposited to extend over the pillar 203, then the insulating material 124 may be polished back (e.g., using a CMP technique).

[0066] FIG. 2V is a side cross-sectional view of an assembly subsequent to recessing the material for the gate electrode 106 of the assembly of FIG. 2U. The material for the gate electrode 106 may be recessed back so that the material for the gate electrode 106 does not contact the S/D contact 104, and so that the gate dielectric 108 may be disposed between the channel 103 and the material for the gate electrode 106. Any suitable technique may be used to recess the material for the gate electrode 106 (e.g., a wet or dry recess).

[0067] FIG. 2W is a side cross-sectional view of an assembly subsequent to patterning the material for the gate electrode 106 of the assembly of FIG. 2V to form the gate electrode 106. As illustrated in FIG. 2W (and FIG. IB), the gate electrode 106 may laterally surround the gate dielectric 108. The patterning of the material for the gate electrode 106 may be performed using any suitable technique (e.g., using a photosensitive resist, exposing and developing the photosensitive resist, then etching away the unwanted material in accordance with the pattern in the resist). As discussed above with reference to the formation of the pillar 203, and as discussed below, the formation of the gate electrode 106 may involve one or multiple sets of etch operations. In some embodiments, the gate electrode 106 may be materially continuous between multiple vertical transistors 100, as discussed below.

[0068] FIG. 2X is a side cross-sectional view of an assembly subsequent to forming additional interconnect structures (e.g., conductive vias 112 and conductive lines 114 for the conductive pathways 165 and 167) on the assembly of FIG. 2W. Insulating material 124 may be disposed around the additional interconnect structures in the assembly of FIG. 2X. Any suitable fabrication techniques may be used to form the additional interconnect structures in the assembly of FIG. 2X (e.g., subtractive, additive, Damascene, dual Damascene, etc.). Additionally, as noted above, the interconnect structure shown in FIG. 2X is simply illustrative, and any desired further fabrication operations may be performed on the assembly of FIG. 2W.

[0069] As noted above, in some embodiments, a quantum dot device 150 may include multiple vertical transistors 100 and multiple quantum dot gates 208. Some of these vertical transistors 100 may be fabricated simultaneously, and may be electrically coupled in any of a number of ways. For example, FIGS. 3A-3D are cross-sectional views of an example quantum dot device 150 including an array of vertical transistors 100 and an array of quantum dot gates 208, in accordance with various embodiments. In particular, FIG. 3A is a "side" cross-sectional view (through the section A-A of FIGS. 3B-3D), FIG. 3B is a "top" cross-sectional view (through the section B-B of FIG. 3A), FIG. 3C is a "top" cross-sectional view (through the section C-C of FIG. 3A), and FIG. 3D is a "top" cross-sectional view (through the section D-D of FIG. 3A). A number of the components of the quantum dot device 150 of FIG. 3 may take the form of any of the embodiments of those components discussed elsewhere herein, and thus these components are not discussed again with reference to FIG. 3 for clarity of illustration.

[0070] In the quantum dot device 150 of FIG. 3, multiple vertical transistors 100 and multiple quantum dot gates 208 may each be arranged in an array. The arrays of the quantum dot device 150 of FIG. 3 may be regular rectangular arrays (e.g., grids), but other arrays of multiple vertical transistors 100 and multiple quantum dot gates 208 may be used. For discussion purposes, the vertical transistors 100 and the quantum dot gates 208 of the quantum dot device 150 of FIG. 3 may be referred to as being arranged in columns 151 and rows 153; these labels are intended to enable a discussion of the relative placement and connections between different ones of the vertical transistors 100 and different ones of the quantum dot gates 208.

[0071] As illustrated in FIG. 3, the vertical transistors 100 in a particular row 153 may share a gate electrode 106. In some embodiments, sharing a gate electrode 106 between multiple vertical transistors 100 may mean that the gate electrodes 106 of the multiple vertical transistors 100 are materially continuous. In some embodiments, the gate electrodes 106 of different ones of the vertical transistors 100 in a particular row 153 may have gate electrodes 106 that are not materially continuous, but that are electrically coupled so that all the gate electrodes 106 in the row 153 have the same voltage at any given time. The gate electrodes 106 in different rows 153 may not be materially continuous, as shown, and the voltages on the gate electrodes 106 in different rows 153 may be independently controllable. [0072] In the embodiment of FIG. 3, different ones of the quantum dot gates 208 may not be directly coupled to each other; in particular, no quantum dot gate electrodes 212 of different quantum dot gates 208 may be materially contiguous. This need not be the case, however, and in other embodiments, different ones of the quantum dot gates 208 may be electrically coupled in any desired manner.

[0073] As illustrated in FIG. 3, the vertical transistors 100 in a particular column 151 may share a conductive line 114 of the conductive pathway 163 in that the S/D contacts 102 of each of the vertical transistors 100 in a particular column 151 are electrically coupled to the same conductive line 114 (and thus have the same voltage at any given time). In some embodiments, as discussed below, the conductive line 114 of the conductive pathway 163 may itself provide the S/D contacts 102 of multiple vertical transistors 100 in a particular column 151. The vertical transistors 100 in different columns 151 may not share a conductive line 114 of the conductive pathway 163, as shown, and the voltages on these conductive lines 114 (and thus on the S/D contacts 102 and their associated quantum dot gates 208) in different columns 151 may be independently controllable.

[0074] The spacing between different ones of the vertical transistors 100 in an array may take any suitable values. For example, in some embodiments, the center-to-center spacing 193 between adjacent vertical transistors in a row 153 may be between 30 nanometers and 300 nanometers (e.g., 50 nanometers). In some embodiments, the center-to-center spacing 195 between adjacent vertical transistors in a column 151 may be between 30 nanometers and 300 nanometers (e.g., 50 nanometers). In some embodiments, the center-to-center spacing 193 and the center-to-center spacing 195 may be equal. The spacing of the vertical transistors 100 may be mirrored by the spacing of the quantum dot gates 208 associated with the vertical transistors 100 (e.g., the vertical transistors 100 and the quantum dot gates 208 may have the same pitch in multiple dimensions).

[0075] FIGS. 4A-4K illustrate various example stages in the manufacture of the quantum dot device 150 of FIGS. 3A-3D, in accordance with various embodiments. However, as noted above, the vertical transistors 100 and quantum dot devices 150 disclosed herein may be formed using any suitable techniques.

[0076] FIG. 4C is a side cross-sectional view of an assembly subsequent to forming an interconnect structure including multiple conductive pathways 163 on the assembly of FIG. 4B so that different ones of the conductive pathways 163 are in conductive contact with different ones of the quantum dot gate electrodes 212. Insulating material 124 may be disposed around the conductive pathways 163 in the assembly of FIG. 4C, and the assembly of FIG. 4C may be formed using any of the techniques discussed above with reference to the assembly of FIG. 2M. FIG. 4D is a top cross- sectional view of the assembly of FIG. 4C through the section D-D of FIG. 4C (such that the view of FIG. 4C is taken through the section A-A of FIG. 4D). As shown in FIG. 4D, the conductive lines 114 of the conductive pathways 163 may take the form of multiple parallel ridges. The interconnect structure shown in FIG. 4C is simply illustrative.

[0077] FIG. 4E is a side cross-sectional view (from the same perspective as FIG. 4C) of an assembly subsequent to providing material for the S/D contact 102, material for the channel 103, and material for the S/D contact 104 on the assembly of FIGS. 4C and 4D. The provision of these materials may take any of the forms discussed above with reference to the assembly of FIG. 2N.

[0078] FIG. 4F is a side cross-sectional view of an assembly subsequent to patterning the material for the S/D contact 104, the material for the channel 103, and the material for the S/D contact 102 of the assembly of FIG. 4E to form multiple pillars 203, each including an S/D contact 104, a channel 103, and an S/D contact 102. FIG. 4G is a top cross-sectional view of the assembly of FIG. 4F (through the section B-B of FIG. 4F) such that the view of FIG. 4F is taken through the section A-A of FIG. 4G. In some embodiments, the pillars 203 may be arranged in an array including rows 153 and columns 151. Pillars 203 in a same column 151 may extend from a same conductive line 114 of the conductive pathways 163, while pillars 203 in different columns 151 may extend from different conductive lines 114. The formation of the pillars 203 may take any of the forms discussed above with reference to FIGS. 20 and 2P. For example, in some embodiments, the formation of the pillars 203 may be performed in a single set of etch operations, while in other embodiments, the material for the S/D contacts 102, the material for the channels 103, and the material for the S/D contacts 104 may first be etched into rows or columns, then etched in the other direction to form the array of pillars 203.

[0079] FIG. 4H is a side cross-sectional view of an assembly subsequent to providing insulating material 124 around the pillars 203 of the assembly of FIGS. 4F and 4G, providing the gate dielectric 108 on side faces of the channels 103, and providing the material for the gate electrode 106. These operations and materials may take the form of any of the embodiments discussed above with reference to FIGS. 2R-2V, for example. FIG. 41 is a top cross-sectional view of the assembly of FIG. 4H (through the section B-B of FIG. 4H) such that the view of FIG. 4H is taken through the section A-A of FIG. 41.

[0080] FIG. 4J is a side cross-sectional view of an assembly subsequent to patterning the material for the gate electrode 106 of the assembly of FIGS. 4H and 41 to form the gate electrodes 106, and providing additional insulating material 124. FIG. 4K is a top cross-sectional view of the assembly of FIG. 4J (through the section B-B of FIG. 4J) such that the view of FIG. 4J is taken through the section A-A of FIG. 4K. As illustrated in FIG. 4K (and FIG. 3B), a gate electrode 106 may laterally surround the gate dielectrics 108 and may be materially continuous for all the vertical transistors 100 in a common row 153, and different rows 153 may have materially discontinuous gate electrodes 106. Thus, the gate electrodes 106 of different vertical transistors 100 in a given row 153 may be electrically "tied," and the conductive lines 114 of the conductive pathways 163 of different vertical transistors 100 in a given column 151 may be electrically "tied." The patterning of the material for the gate electrodes 106 may be performed using any of the techniques discussed above with reference to FIG. 2W, for example. Additional interconnect structures (e.g., conductive vias 112 and conductive lines 114 for the conductive pathways 165 and 167) may be formed on the assembly of FIGS. 4J and 4K to form the quantum dot device 150 of FIG. 5 (e.g., using any of the techniques discussed above with reference to FIG. 2X). Additionally, any desired further fabrication operations may also be performed.

[0081] In the embodiments discussed above with reference to FIGS. 3 and 4, the conductive lines 114 of the conductive pathways 163 are patterned prior to patterning of the S/D contacts 102. In some embodiments, the conductive lines 114 of the conductive pathways 163 may be patterned as part of a common set of patterning operations with at least the initial patterning of the S/D contacts 102, and thus the conductive lines 114 of the conductive pathways 163 may be said to be "self- aligned" with the S/D contacts 102.

[0082] FIGS. 5A-5E are cross-sectional views of an example quantum dot device 150 including an array of vertical transistors 100 in which the conductive lines 114 of the conductive pathways 163 take the form of parallel ridges with side faces 171 that are substantially aligned with side faces 173 of the S/D contacts 102, in accordance with various embodiments. FIG. 5A is a "side" cross-sectional view (through the section A-A of FIGS. 5B-5D), FIG. 5B is a "top" cross-sectional view (through the section B-B of FIG. 5A), FIG. 5C is a "top" cross-sectional view (through the section C-C of FIG. 5A), and FIG. 5D is a "top" cross-sectional view (through the section D-D of FIG. 5A). FIG. 5E is a detail view of a portion of FIG. 5A, including reference numerals labeling the side faces of various components of a vertical transistor 100. A number of the components of the quantum dot device 150 of FIG. 5 may take the form of any of the embodiments of those components discussed elsewhere herein, and thus these components are not discussed again with reference to FIG. 5 for clarity of illustration.

[0083] In some embodiments, as illustrated in FIG. 5, the self-alignment may extend all the way up the pillars 203, with the side faces 171 of the conductive lines 114 being aligned with the side faces 173 of the S/D contacts 102, the side faces 175 of the channels 103, and the side faces 177 of the S/D contacts 104.

[0084] In embodiments in which the conductive lines 114 of the conductive pathways 163 are patterned along with the S/D contacts 102, the insulating material 124 disposed proximate to the side faces 171, and the insulating material 124 proximate to the side faces 173, may be materially continuous and deposited as part of a single operation. In other words, when the conductive lines 114 of the conductive pathways 163 are patterned prior to initial patterning of the S/D contacts 102, the insulating material 124 in the same layer as the conductive lines 114 (e.g., the insulating material 124 proximate to the side faces 171) may be deposited in a first set of operations, then the S/D contacts 102 and additional insulating material 124 in the same "layer" as the S/D contacts 102 (e.g., the insulating material 124 proximate to the side faces 173) may be deposited in a second set of operations. In such an embodiment of the quantum dot device 150, there may be a visible material interface between the insulating material 124 in the same layer as the conductive lines 114 and the insulating material in the same layer as the S/D contacts 102. By contrast, when the conductive lines 114 are patterned in the same set of patterning operations as the initial patterning of the S/D contacts 102, the insulating material 124 may be provided around the conductive lines 114 and the S/D contacts 102 in one deposition operation, and thus there may be no such material interface.

[0085] FIGS. 6A-6H illustrate various example stages in the manufacture of the quantum dot device of FIGS. 5A-5E, in accordance with various embodiments. However, as noted above, the quantum dot devices 150 disclosed herein may be formed using any suitable techniques. The operations of FIG. 6 may be performed on a starting assembly including multiple quantum dot gates 208, like the assembly of FIGS. 4A and 4B, but these assemblies are not shown in FIG. 6 for simplicity of illustration.

[0086] FIG. 6A is a side cross-sectional view of an assembly subsequent to forming an interconnect structure including multiple conductive vias 112 (which will become part of corresponding multiple conductive pathways 163, as discussed below). As noted above, the assembly of FIG. 6A may be formed on the assembly of FIGS. 4A and 4B (not shown for simplicity of illustration) so that different ones of the conductive vias 112 are in conductive contact with different ones of the quantum dot gate electrodes 212. Insulating material 124 may be disposed around the conductive vias 112 in the assembly of FIG. 6A, and the assembly of FIG. 6A may be formed using any of the techniques discussed above with reference to the assembly of FIG. 2M. The interconnect structure shown in FIG. 6A is simply illustrative.

[0087] FIG. 6B is a side cross-sectional view of an assembly subsequent to providing material for the conductive lines 114, material for the S/D contacts 102, material for the channels 103, and material for the S/D contacts 104 on the assembly of FIG. 6A. The provision of these materials may take any of the forms discussed above with reference to the assembly of FIG. 2N, including the use of any suitable technique for depositing the material for the conductive lines 114. [0088] FIG. 6C is a side cross-sectional view of an assembly subsequent to patterning the material for the conductive lines 114, the material for the S/D contact 104, the material for the channel 103, and the material for the S/D contact 102 of the assembly of FIG. 6B to form multiple ridges 205, each including a conductive line 114, material for an S/D contact 104, material for a channel 103, and material for an S/D contact 102. FIG. 6D is a top cross-sectional view of the assembly of FIG. 6C (through the section B-B of FIG. 6C) such that the view of FIG. 6C is taken through the section A-A of FIG. 6D, and FIG. 6E is a top cross-sectional view of the assembly of FIG. 6C (through the section D-D of FIG. 6C) such that the view of FIG. 6C is taken through the section A-A of FIG. 6E.

[0089] FIG. 6F is a side cross-sectional view (from the same perspective as FIG. 6C) of an assembly subsequent to performing additional patterning to form pillars 203 from the ridges 205 of the assembly of FIGS. 6C-6E. FIG. 6G is a top cross-sectional view of the assembly of FIG. 6F (through the section B-B of FIG. 6F) such that the view of FIG. 6F is taken through the section A-A of FIG. 6G, and FIG. 6H is a top cross-sectional view of the assembly of FIG. 6F (through the section D-D of FIG. 6F) such that the view of FIG. 6F is taken through the section A-A of FIG. 6H. The pillars 203 include the S/D contacts 102, the channels 103, and the S/D contacts 104, and are arranged in an array of rows 153 and columns 151, as discussed above. The patterning illustrated in FIGS. 6F-6H "stops" at the S/D contacts 102, and the conductive lines 114 of the assembly of FIG. 6C are not further patterned to form the assembly of FIG. 6F (as illustrated in FIGS. 6G and 6H). The formation of the pillars 203 may take any of the forms discussed above with reference to FIGS. 20 and 2P, for example. The assembly of FIG. 6F may be further processed to provide gate dielectric 108, gate electrodes 106, and conductive pathways 165 and 167 to form the quantum dot device 150 of FIG. 5 (e.g., in accordance with any of the techniques discussed above with reference to FIGS. 4H-4K). Additionally, any desired further fabrication operations may also be performed.

[0090] In the embodiments illustrated in FIGS. 1, 3, and 5, the S/D contacts 102 take the form of "pedestals" extending away from conductive lines 114 of the conductive pathways 163. In some embodiments, the conductive lines 114 may themselves provide the S/D contacts 102; in other words, the conductive lines 114 may directly contact the channels 103, without any intervening material. FIGS. 7A-7D are cross-sectional views of an example quantum dot device 150 including an array of vertical transistors 100 in which the S/D contacts 102 are provided by the conductive lines 114 of the conductive pathways 163, in accordance with various embodiments. FIG. 7A is a "side" cross-sectional view (through the section A-A of FIGS. 7B-7D), FIG. 7B is a "top" cross-sectional view (through the section B-B of FIG. 7A), FIG. 7C is a "top" cross-sectional view (through the section C-C of FIG. 7A), and FIG. 7D is a "top" cross-sectional view (through the section D-D of FIG. 7A). A number of the components of the quantum dot device 150 of FIG. 7 may take the form of any of the embodiments of those components discussed elsewhere herein, and thus these components are not discussed again with reference to FIG. 7 for clarity of illustration. Any suitable techniques may be used to manufacture the quantum dot device 150 of FIG. 7. For example, the quantum dot device 150 of FIG. 7 may be manufactured substantially in accordance with the operations discussed above with reference to FIG. 6, but the separate material layer for the S/D contact 102 may be omitted; instead, the material for the conductive lines 114 may abut the material for the channels 103.

[0091] FIGS. 8A-8C illustrate various examples of quantum well stacks 246 that may provide the quantum well stacks 246 of any of the embodiments of the quantum dot devices 150 disclosed herein. In some embodiments, the layers of the quantum well stacks 246 may be grown on a substrate (e.g., a silicon or germanium wafer), and on each other, by epitaxy. Generally, the quantum well stack 246 included in a quantum dot device 150 may include one quantum well layer 252 or more than two quantum well layers 252; elements may be omitted from the quantum well stacks 246, or added to the quantum well stacks 246, discussed with reference to FIG. 8 to achieve such embodiments, as appropriate. Layers other than the quantum well layer(s) 252 in a quantum well stack 246 may have higher threshold voltages for conduction than the quantum well layer(s) 252 so that when the quantum well layer(s) 252 are biased at their threshold voltages, the quantum well layer(s) 252 conduct and the other layers of the quantum well stack 246 do not. This may avoid parallel conduction in both the quantum well layer(s) 252 and the other layers, and thus avoid compromising the strong mobility of the quantum well layer(s) 252 with conduction in layers having inferior mobility. In some embodiments, silicon used in a quantum well stack 246 may be isotopically enriched 28Si. In some embodiments, germanium used in a quantum well stack 246 may be isotopically enriched 70Ge, 72Ge, or 74Ge.

[0092] FIG. 8A is a cross-sectional view of a quantum well stack 246 including only a quantum well layer 252. The quantum well layer 252 may be formed of a material such that, during operation of the quantum dot device 150, a 2DEG may form in the quantum well layer 252 proximate to the upper surface of the quantum well layer 252. The quantum dot gate dielectric 214 may be disposed on the upper surface of the quantum well layer 252. In some embodiments, the quantum well layer 252 of FIG. 8A may be formed of intrinsic silicon, and the quantum dot gate dielectric 214 may be formed of silicon oxide; in such an arrangement, during use of the quantum dot device 150, a 2DEG may form in the intrinsic silicon at the interface between the intrinsic silicon and the silicon oxide. Embodiments in which the quantum well layer 252 of FIG. 8A is formed of intrinsic silicon may be particularly advantageous for electron-type quantum dot devices 150. In some embodiments, the quantum well layer 252 of FIG. 8A may be formed of intrinsic germanium, and the quantum dot gate dielectric 214 may be formed of germanium oxide; in such an arrangement, during use of the quantum dot device 150, a 2DEG may form in the intrinsic germanium at the interface between the intrinsic germanium and the germanium oxide. Such embodiments may be particularly

advantageous for hole-type quantum dot devices 150. In some embodiments, the quantum well layer 252 may be strained, while in other embodiments, the quantum well layer 252 may not be strained. The thicknesses (i.e., z-heights) of the layers in the quantum well stack 246 of FIG. 8A may take any suitable values. For example, in some embodiments, the thickness of the quantum well layer 252 (e.g., intrinsic silicon or germanium) may be between 0.8 microns and 1.2 microns.

[0093] FIG. 8B is a cross-sectional view of a quantum well stack 246 including a quantum well layer 252 and a barrier layer 254. The quantum well stack 246 may be disposed on a substrate such that the barrier layer 254 is disposed between the quantum well layer 252 and the substrate. The barrier layer 254 may provide a potential barrier between the quantum well layer 252 and the substrate. As discussed above with reference to FIG. 8A, the quantum well layer 252 of FIG. 8B may be formed of a material such that, during operation of the quantum dot device 150, a 2DEG may form in the quantum well layer 252 proximate to the upper surface of the quantum well layer 252. For example, in some embodiments in which the substrate is formed of silicon, the quantum well layer 252 of FIG. 8B may be formed of silicon, and the barrier layer 254 may be formed of silicon germanium. The germanium content of this silicon germanium may be 20-80% (e.g., 30%). In some embodiments in which the quantum well layer 252 is formed of germanium, the barrier layer 254 may be formed of silicon germanium (with a germanium content of 20-80% (e.g., 70%)). The thicknesses (i.e., z- heights) of the layers in the quantum well stack 246 of FIG. 8B may take any suitable values. For example, in some embodiments, the thickness of the barrier layer 254 (e.g., silicon germanium) may be between 0 nanometers and 400 nanometers. In some embodiments, the thickness of the quantum well layer 252 (e.g., silicon or germanium) may be between 5 nanometers and 30 nanometers.

[0094] FIG. 8C is a cross-sectional view of a quantum well stack 246 including a quantum well layer 252 and a barrier layer 254-1, as well as a buffer layer 276 and an additional barrier layer 254-2. The quantum well stack 246 may be disposed on a substrate such that the buffer layer 276 is disposed between the barrier layer 254-1 and the substrate. The buffer layer 276 may be formed of the same material as the barrier layer 254, and may be present to trap defects that form in this material as it is grown on the substrate. In some embodiments, the buffer layer 276 may be grown under different conditions (e.g., deposition temperature or growth rate) from the barrier layer 254-1. In particular, the barrier layer 254-1 may be grown under conditions that achieve fewer defects than the buffer layer 276. In some embodiments in which the buffer layer 276 includes silicon germanium, the silicon germanium of the buffer layer 276 may have a germanium content that varies from the substrate to the barrier layer 254-1; for example, the silicon germanium of the buffer layer 276 may have a germanium content that varies from zero percent at the substrate to a nonzero percent (e.g., 30%) at the barrier layer 254-1. The thicknesses (i.e., z-heights) of the layers in the quantum well stack 246 of FIG. 8C may take any suitable values. For example, in some embodiments, the thickness of the buffer layer 276 (e.g., silicon germanium) may be between 0.3 microns and 4 microns (e.g., 0.3-2 microns, or 0.5 microns). In some embodiments, the thickness of the barrier layer 254-1 (e.g., silicon germanium) may be between 0 nanometers and 400 nanometers. In some embodiments, the thickness of the quantum well layer 252 (e.g., silicon or germanium) may be between 5 nanometers and 30 nanometers (e.g., 10 nanometers). The barrier layer 254-2, like the barrier layer 254-1, may provide a potential energy barrier around the quantum well layer 252, and may take the form of any of the embodiments of the barrier layer 254-1. In some embodiments, the thickness of the barrier layer 254-2 (e.g., silicon germanium) may be between 25 nanometers and 75 nanometers (e.g., 32 nanometers).

[0095] As discussed above with reference to FIG. 8B, the quantum well layer 252 of FIG. 8C may be formed of a material such that, during operation of the quantum dot device 150, a 2DEG may form in the quantum well layer 252 proximate to the upper surface of the quantum well layer 252. For example, in some embodiments in which the substrate is formed of silicon, the quantum well layer 252 of FIG. 8C may be formed of silicon, and the barrier layer 254-1 and the buffer layer 276 may be formed of silicon germanium. In some such embodiments, the silicon germanium of the buffer layer 276 may have a germanium content that varies from the substrate to the barrier layer 254-1; for example, the silicon germanium of the buffer layer 276 may have a germanium content that varies from zero percent at the substrate to a nonzero percent (e.g., 30%) at the barrier layer 254-1. The barrier layer 254-1 may in turn have a germanium content equal to the nonzero percent. In other embodiments, the buffer layer 276 may have a germanium content equal to the germanium content of the barrier layer 254-1 but may be thicker than the barrier layer 254-1 to absorb the defects that arise during growth.

[0096] In some embodiments, the quantum well layer 252 of FIG. 8C may be formed of germanium, and the buffer layer 276 and the barrier layer 254-1 may be formed of silicon germanium. In some such embodiments, the silicon germanium of the buffer layer 276 may have a germanium content that varies from the substrate to the barrier layer 254-1; for example, the silicon germanium of the buffer layer 276 may have a germanium content that varies from zero percent at the substrate to a nonzero percent (e.g., 70%) at the barrier layer 254-1. The barrier layer 254-1 may in turn have a germanium content equal to the nonzero percent. In other embodiments, the buffer layer 276 may have a germanium content equal to the germanium content of the barrier layer 254-1 but may be thicker than the barrier layer 254-1 to absorb the defects that arise during growth. In some embodiments of the quantum well stack 246 of FIG. 8C, the buffer layer 276 and/or the barrier layer 254-2 may be omitted.

[0097] As noted above, in some embodiments, the vertical transistors 100 disclosed herein may be included in a quantum dot device 150 with word lines and bit lines. FIG. 9 is a perspective view of a portion of such a quantum dot device 150, in accordance with various embodiments. FIG. 9 is a simplified representation, and the structures therein may take the form of any of the embodiments discussed herein (e.g., with reference to FIGS. 1-8 and 10). The quantum dot device 150 of FIG. 9 may be a cross-point array including quantum dot gate cells 131 located at the intersections of conductive lines 145 and conductive lines 143. Conductive vias (not shown) to the conductive lines 145 and the conductive lines 143 may be made at the "edges" of the quantum dot device 150. In some embodiments, the conductive lines 143 may be word lines and the conductive lines 145 may be bit lines, for example; for clarity of discussion, this terminology may be used herein to refer to the conductive lines 143 and the conductive lines 145.

[0098] In the embodiments illustrated in FIG. 9, the word lines 143 may be parallel to each other and may be arranged perpendicularly to the bit lines 145 (which themselves may be parallel to each other), but any other suitable arrangement may be used. The word lines 143 and/or the bit lines 145 may be formed of any suitable conductive material, such as a metal (e.g., tungsten, copper, titanium, or aluminum or another superconductor). In some embodiments, the quantum dot device 150 depicted in FIG. 9 may be a portion (e.g., a level) of a three-dimensional array in which other cross-point arrays like the cross-point array of FIG. 9 are located at different levels (e.g., above or below each other).

[0099] Each quantum dot gate cell 131 may include a quantum dot gate 208 coupled in series with an associated vertical transistor 100. Generally, electrical signals may be provided to a quantum dot gate 208 to generate a qubit with a desired spin state (in a quantum well stack 246), create a barrier between such qubits, or allow multiple qubits to interact, under the control of the vertical transistor 100. In the embodiment of FIG. 9, the S/D contact 102 may be coupled between the channel 103 and the quantum dot gate 208. The bit lines 145 may be provided by the conductive lines 114 of the conductive pathways 165 of the quantum dot devices 150 discussed herein, and the word lines 143 may be provided by the gate electrodes 106 of the quantum dot devices 150 discussed herein.

[0100] Any of the quantum dot devices 150 disclosed herein may include one or more magnet lines. As used herein, a "magnet line" refers to a magnetic-field-generating structure to influence (e.g., change, reset, scramble, or set) the spin states of quantum dots formed in the quantum well stack 246. One example of a magnet line, as discussed herein, is a conductive pathway that is proximate to an area of quantum dot formation and selectively conductive of a current pulse that generates a magnetic field to influence a spin state of a quantum dot in the area.

[0101] For example, FIG. 10 is a side cross-sectional view of a quantum dot device 150 including a magnet line 121; the magnet line 121 may extend into and out of the plane of the drawing. A magnet line 121 may be formed of a conductive material, and may be used to conduct current pulses that generate magnetic fields to influence the spin states of one or more of the quantum dots that may form in the quantum dot device 150. Alternatively or additionally, a magnet line 121 may be formed of a magnetic material (e.g., cobalt) and may exert a "permanent" magnetic field. In some embodiments, a magnet line 121 may conduct a pulse to reset (or "scramble") quantum dot spins. In some embodiments, a magnet line 121 may conduct a pulse to initialize an electron in a quantum dot in a particular spin state. In some embodiments, a magnet line 121 may conduct current to provide a continuous, oscillating magnetic field to which the spin of a qubit may couple. A magnet line 121 may provide any suitable combination of these embodiments, or any other appropriate functionality.

[0102] In some embodiments, a magnet line 121 may be formed of copper. In some embodiments, a magnet line 121 may be formed of a superconductor, such as aluminum. In some embodiments, a magnet line 121 may be formed of a magnetic material. For example, a magnetic material (such as cobalt) may be deposited in a trench in the insulating material 124 to provide a permanent magnetic field in the quantum dot device 150. A magnet line 121 may have any suitable dimensions. For example, the magnet line 121 may have a thickness and/or width between 25 nanometers and 100 nanometers. In some embodiments, the width and thickness of a magnet line 121 may be equal to the width and thickness, respectively, of other conductive lines in the quantum dot device 150 used to provide electrical interconnects (e.g., the conductive lines 114), and may be formed using any processes known for forming conductive lines (e.g., plating in a trench, followed by planarization, or a semi-additive process). The magnet line 121 illustrated in FIG. 10 is substantially linear, but this need not be the case; magnet lines 121 may take any suitable shape. Conductive vias (not shown) may contact the magnet lines 121 at desired locations.

[0103] In some embodiments, a quantum dot device 150 may include one magnet line 121, or no magnet lines 121; in other embodiments, a quantum dot device 150 may include two, three, four, or more magnet lines 121. Magnet lines 121 included in a quantum dot device 150 may be oriented in any desired manner relative to the quantum dot gates 208 or other structural features of the quantum dot device 150; for example, one or more magnet lines 121 may be oriented from left to right according to the perspective of FIG. 10, in addition to or instead of one or more magnet lines 121 oriented in and out of the plane of the drawing of FIG. 10. [0104] FIG. 11 is a flow diagram of an illustrative method 1050 of operating a quantum dot device, in accordance with various embodiments. Although the operations discussed below with reference to the method 1050 (and the other methods disclosed herein) are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method 1050 (and the other methods disclosed herein) may be illustrated with reference to one or more of the embodiments discussed above, but the method 1050 may be used to operate any suitable quantum dot device (including any suitable ones of the embodiments disclosed herein).

[0105] At 1052, electrical signals to an array of quantum dot gates may be controlled by a corresponding array of vertical transistors to draw carriers into a quantum well stack. In some embodiments, a bit line is in contact with an S/D contact of individual vertical transistors, and a word line of the quantum dot device is in contact with a gate of individual vertical transistors (e.g., as discussed above with reference to FIG. 9); an individual one of the quantum dot gate electrodes may be "addressed" (e.g., electrical signals may be selectively applied to that individual quantum dot gate electrode) using the word lines and bit lines coupled to the vertical transistor associated with the quantum dot gate. For example, a quantum dot gate cell 131 may include a quantum dot gate 208 and a vertical transistor 100; the vertical transistor 100 may control electrical signals to the quantum dot gate 208 to draw carriers into the quantum well stack.

[0106] At 1054, electrical signals to the array of quantum dot gates may be controlled by the array of corresponding vertical transistors to confine one or more carriers in the quantum well stack under at least some of the quantum dot gates. For example, a quantum dot gate cell 131 may include a quantum dot gate 208 and a vertical transistor 100; the vertical transistor 100 may control electrical signals to the quantum dot gate 208 to confine one or more carriers in the quantum well stack under at least some of the quantum dot gates (e.g., by addressing desired ones of the quantum dot gates 208 via their associated vertical transistors 100 and word lines/bit lines).

[0107] The quantum dot devices 150 disclosed herein may be included in any suitable apparatus. FIG. 12 shows top views of a wafer 450 and dies 452 that may be formed from the wafer 450; the dies 452 may include any of the quantum dot devices 150 disclosed herein. The wafer 450 may include semiconductor material and may include one or more dies 452 having conventional and quantum dot device elements formed on a surface of the wafer 450. Each of the dies 452 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum dot device. After the fabrication of the semiconductor product is complete, the wafer 450 may undergo a singulation process in which each of the dies 452 is separated from one another to provide discrete "chips" of the semiconductor product. A die 452 may include one or more quantum dot devices 150 and/or supporting circuitry to route electrical signals to the quantum dot devices, as well as any other integrated circuit (IC) components. In some embodiments, the wafer 450 or the die 452 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 452. For example, a memory array formed by multiple memory devices may be formed on a same die 452 as a processing device (e.g., the processing device 2002 of FIG. 14) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0108] FIG. 13 is a cross-sectional side view of a device assembly 400 that may include any of the embodiments of the quantum dot devices 150 disclosed herein. The device assembly 400 includes a number of components disposed on a circuit board 402. The device assembly 400 may include components disposed on a first face 440 of the circuit board 402 and an opposing second face 442 of the circuit board 402; generally, components may be disposed on one or both faces 440 and 442.

[0109] In some embodiments, the circuit board 402 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 402. In other embodiments, the circuit board 402 may be a package substrate or flexible board.

[0110] The device assembly 400 illustrated in FIG. 13 includes a package-on-interposer structure 436 coupled to the first face 440 of the circuit board 402 by coupling components 416. The coupling components 416 may electrically and mechanically couple the package-on-interposer structure 436 to the circuit board 402, and may include solder balls (as shown in FIG. 13), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0111] The package-on-interposer structure 436 may include a package 420 coupled to an interposer 404 by coupling components 418. The coupling components 418 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 416. Although a single package 420 is shown in FIG. 13, multiple packages may be coupled to the interposer 404; indeed, additional interposers may be coupled to the interposer 404. The interposer 404 may provide an intervening substrate used to bridge the circuit board 402 and the package 420. The package 420 may be a quantum dot device package (e.g., a package that includes one or more quantum dot devices 150) or may be a conventional IC package, for example. In some embodiments, the package 420 may include a quantum dot device die (e.g., a die that includes one or more quantum dot devices 150) coupled to a package substrate (e.g., by flip chip connections). Generally, the interposer 404 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 404 may couple the package 420 (e.g., a die) to a ball grid array (BGA) of the coupling components 416 for coupling to the circuit board 402. In the embodiment illustrated in FIG. 13, the package 420 and the circuit board 402 are attached to opposing sides of the interposer 404; in other embodiments, the package 420 and the circuit board 402 may be attached to a same side of the interposer 404. In some embodiments, three or more components may be interconnected by way of the interposer 404.

[0112] The interposer 404 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 404 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 404 may include metal interconnects 408 and vias 410, including but not limited to through-silicon vias (TSVs) 406. The interposer 404 may further include embedded devices 414, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as F devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 404. The package-on-interposer structure 436 may take the form of any of the package-on-interposer structures known in the art.

[0113] The device assembly 400 may include a package 424 coupled to the first face 440 of the circuit board 402 by coupling components 422. The coupling components 422 may take the form of any of the embodiments discussed above with reference to the coupling components 416, and the package 424 may take the form of any of the embodiments discussed above with reference to the package 420. The package 424 may be a quantum dot device package (e.g., a package that includes one or more quantum dot devices 150) or may be a conventional IC package, for example. In some embodiments, the package 424 may include a quantum dot device die (e.g., a die that includes one or more quantum dot devices 150) coupled to a package substrate (e.g., by flip chip connections).

[0114] The device assembly 400 illustrated in FIG. 13 includes a package-on-package structure 434 coupled to the second face 442 of the circuit board 402 by coupling components 428. The package- on-package structure 434 may include a package 426 and a package 432 coupled together by coupling components 430 such that the package 426 is disposed between the circuit board 402 and the package 432. The coupling components 428 and 430 may take the form of any of the embodiments of the coupling components 416 discussed above, and the packages 426 and 432 may take the form of any of the embodiments of the package 420 discussed above. Each of the packages 426 and 432 may be a quantum dot device package (e.g., a package that includes one or more quantum dot devices 150) or may be a conventional IC package, for example. In some

embodiments, one or both of the packages 426 and 432 may take the form of any of the

embodiments of a quantum dot device package (e.g., a package that includes one or more quantum dot devices 150) disclosed herein, and may include a die coupled to a package substrate (e.g., by flip chip connections).

[0115] FIG. 14 is a block diagram of an example quantum computing device 2000 that may include any of the quantum dot devices 150 disclosed herein. A number of components are illustrated in FIG. 14 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all the components included in the quantum computing device 2000 may be attached to one or more PCBs (e.g., a motherboard). In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 14, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled. In another set of examples, the quantum computing device 2000 may not include an audio input device 2024 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2024 or audio output device 2008 may be coupled.

[0116] The quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). The quantum processing device 2026 may include one or more of the quantum dot devices 150 disclosed herein, and may perform data processing by performing operations on the quantum dots that may be generated in the quantum dot devices 150, and monitoring the result of those operations. For example, as discussed above, different quantum dots may be allowed to interact, the quantum states of different quantum dots may be set or transformed, and the quantum states of quantum dots may be read (e.g., by another quantum dot). The quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.

[0117] As noted above, the processing device 2002 may include a non-quantum processing device 2028. In some embodiments, the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026. For example, the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, control the performance of any of the operations discussed above with reference to FIGS. 6A-C, etc. The non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026. For example, the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components. The non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

[0118] The quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004. In some embodiments, the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM). [0119] The quantum computing device 2000 may include a cooling apparatus 2030. The cooling apparatus 2030 may maintain the quantum processing device 2026 at a predetermined low temperature during operation to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some

embodiments, the temperature may be 10 Kelvin or less (e.g., 5 Kelvin or less, or 2 Kelvin or less). In some embodiments, the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature. The cooling apparatus 2030 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.

[0120] In some embodiments, the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data using modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0121] The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for

Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless

communications (such as AM or FM radio transmissions).

[0122] In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.

[0123] The quantum computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).

[0124] The quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0125] The quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0126] The quantum computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above). The audio input device 2024 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (M I DI) output).

[0127] The quantum computing device 2000 may include a GPS device 2018 (or corresponding interface circuitry, as discussed above). The GPS device 2018 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.

[0128] The quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0129] The quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0130] The quantum computing device 2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0131] The following paragraphs provide various examples of the embodiments disclosed herein.

[0132] Example 1 is a quantum dot device, including: a quantum well stack; a quantum dot gate electrode in a first layer above the quantum well stack; and a transistor in a second layer above the first layer, wherein the transistor includes a first source/drain (S/D) contact, a second S/D contact, a channel, a transistor gate electrode, and a transistor gate dielectric between the transistor gate electrode and the channel, the first S/D contact is between the second S/D contact and the first layer, and the first S/D contact is electrically coupled to the quantum dot gate electrode.

[0133] Example 2 may include the subject matter of Example 1, and may further specify that the channel includes a thin film material.

[0134] Example 3 may include the subject matter of any of Examples 1-2, and may further specify that the transistor gate dielectric wraps around the channel, and the transistor gate electrode wraps around the gate dielectric.

[0135] Example 4 may include the subject matter of any of Examples 1-3, and may further specify that the first S/D contact includes a semiconductor and an n-type dopant.

[0136] Example 5 may include the subject matter of any of Examples 1-4, and may further specify that the first S/D contact includes a metal.

[0137] Example 6 may include the subject matter of any of Examples 1-5, and may further specify that the quantum dot gate electrode is a first quantum dot gate electrode, the transistor is a first transistor, and the quantum dot device further includes: a second quantum dot gate electrode in the first layer; and a second transistor in the second layer, wherein: the second transistor includes a first S/D contact, a second S/D contact, a channel, a transistor gate electrode, and a transistor gate dielectric between the transistor gate electrode of the second transistor and the channel of the second transistor, the transistor gate electrode of the second transistor is materially continuous with the gate electrode of the first transistor, and the first S/D contact of the second transistor is electrically coupled to the second quantum dot gate electrode.

[0138] Example 7 may include the subject matter of Example 6, and may further specify that the quantum dot device further includes: a third quantum dot gate electrode in the first layer; and a third transistor in the second layer, wherein: the third transistor includes a first S/D contact, a second S/D contact, a channel, a transistor gate electrode, and a transistor gate dielectric between the transistor gate electrode of the third transistor and the channel of the third transistor, the transistor gate electrode of the third transistor is not materially continuous with the transistor gate electrodes of the first transistor and the second transistor, and the first S/D contact of the third transistor is electrically coupled to the third quantum dot gate electrode.

[0139] Example 8 may include the subject matter of Example 7, and may further specify that the first S/D contact of the first transistor is electrically continuous with the first S/D contact of the third transistor.

[0140] Example 9 may include the subject matter of any of Examples 1-8, and may further specify that a bit line is coupled to the first S/D contact or the second S/D contact, and a word line is coupled to the transistor gate electrode.

[0141] Example 10 may include the subject matter of any of Examples 1-9, and may further specify that the quantum well stack includes a layer of silicon or a layer of germanium, and the layer of silicon or the layer of germanium is in contact with a layer of quantum dot gate dielectric between the quantum dot gate electrode and the layer of silicon or the layer of germanium.

[0142] Example 11 may include the subject matter of any of Examples 1-10, and may further specify that the quantum well stack includes silicon and germanium.

[0143] Example 12 may include the subject matter of Example 11, and may further specify that the quantum well stack includes a quantum well layer including a layer of silicon or a layer of germanium, the quantum well stack includes a barrier layer including silicon and germanium, and the barrier layer is between the quantum well layer and the quantum dot gate electrode.

[0144] Example 13 may include the subject matter of any of Examples 1-12, and may further include an accumulation region.

[0145] Example 14 may include the subject matter of any of Examples 1-13, and may further include a magnet line. [0146] Example 15 is a method of manufacturing a quantum dot device, including: forming a quantum well stack; forming a quantum dot gate electrode above the quantum well stack; forming a layer of conductive material above the quantum dot gate electrode; forming a layer of thin film semiconductor material on the conductive material; patterning the thin film semiconductor material to form a plurality of pillars; forming a layer of transistor gate dielectric on side faces of the pillars; and forming a transistor gate electrode in contact with the transistor gate dielectric.

[0147] Example 16 may include the subject matter of Example 15, and may further specify that the thin film semiconductor material includes an amorphous semiconductor, a polycrystalline semiconductor, a crystalline semiconductor, an amorphous semiconductor oxide, a polycrystalline semiconductor oxide, or a crystalline semiconductor oxide.

[0148] Example 17 may include the subject matter of any of Examples 15-16, and may further include patterning the conductive material with an etch process subsequent to patterning the thin film semiconductor material.

[0149] Example 18 may include the subject matter of Example 17, and may further include providing an insulating material around the patterned conductive material, wherein the gate electrode is provided on the insulating material.

[0150] Example 19 may include the subject matter of any of Examples 15-18, and may further specify that the thin film semiconductor material has a thickness between 10 nanometers and 100 nanometers.

[0151] Example 20 may include the subject matter of any of Examples 15-19, and may further include patterning the transistor gate electrode such that a portion of the transistor gate electrode is materially continuous around multiple ones of the pillars, but is not materially continuous around all the pillars.

[0152] Example 21 may include the subject matter of any of Examples 15-20, and may further include forming an accumulation region in the quantum well stack.

[0153] Example 22 is a method of operating a quantum dot device, including: controlling current to an array of quantum dot gate electrodes, through an array of transistors, to draw carriers into a quantum well stack under the array of quantum dot gate electrodes; and controlling current to the array of quantum dot electrodes, through the array of transistors, to confine one or more carriers in the quantum well stack under at least some of the quantum dot gate electrodes; wherein the array of transistors is above the array of quantum dot gate electrodes.

[0154] Example 23 may include the subject matter of Example 22, and may further specify that each transistor in the array of transistors is associated with one word line and one bit line. [0155] Example 24 may include the subject matter of any of Examples 22-23, and may further include controlling a current through one or more magnet lines to change a spin state of a carrier under at least one of the quantum dot gate electrodes.

[0156] Example 25 is a quantum computing device, including: a quantum processing device, wherein the quantum processing device includes a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of transistors above the array of quantum dot gate electrodes, wherein the array of quantum dot gate electrodes and the array of transistors are each arranged in a grid, and the grids have a same pitch.

[0157] Example 26 may include the subject matter of Example 25, and may further include: a non- quantum processing device, coupled to the quantum processing device, to control electrical signals applied to the quantum dot gate electrodes; and a memory device to store data generated by the quantum processing device.

[0158] Example 27 may include the subject matter of Example 26, and may further specify that the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

[0159] Example 28 may include the subject matter of any of Examples 25-27, and may further include a plurality of word lines, and may further specify that different individual word lines strap together gates in different individual rows of transistors in the array of transistors.

[0160] Example 29 may include the subject matter of any of Examples 25-28, and may further include a cooling apparatus to maintain a temperature of the quantum processing device below 10

Kelvin.