This application claims the benefit of European Patent Application EP22382467.3 filed 13 May 2022.

The present disclosure relates to digital communication coding methods and to systems, computing systems and computing programs suitable for performing such methods.

The present disclosure further relates to methods, systems, computing systems and computing programs to encode and decode data in digital communications.

BACKGROUND

As known to the person skilled in the art a low-density parity-check (LDPC) code C is a linear code determined by a sparse parity-check matrix H having a small number of 1s per column. The parity-check matrix H may be represented by a bipartite Tanner graph wherein each column of H is represented by a transmitted variable node, each row by a check node, and each “1” in H by a graph edge connecting the variable node and check node that correspond to the column-row location of the “1”. Each check or constraint node defines a parity check operation. The fraction of a transmission that carries information is called the rate of the code. An LDPC code may be encoded by deriving an appropriate generator matrix G from its parity-check matrix H. An LDPC code may be decoded efficiently using well-known iterative decoding algorithms that pass messages along edges of the code’s Tanner graph from variable nodes to check nodes and vice- versa until convergence is obtained. However, for very long codes, such iterative processes may by costly and lower complexity algorithms are also well known, which do perform efficiently for certain long LDPC codes in which the column weight is relatively high.

A quasi-cyclic low-density parity-check matrix is completely determined by a reduced matrix H _rep whose (i, j) entry (H _rep )ij consists of either the empty set or a small subset of numbers between zero and b — 1 , where b is the block size. The low-density parity-check matrix H is recovered from the reduced matrix H _rep by replacing each number r e (H _rep )ij by the identity matrix of dimension b shifted cyclically r bits to the right and by replacing the empty set by the square zero matrix of dimension b. A quasi-cyclic generator matrix G in standard form may be found for the LDPC code by Gaussian elimination on the blocks. This allows fast encoding of the data bits as explained in [Z. Li, L. Chen, L. Zeng, W.Fong and S. Lin, Efficient encoding of quasi-cyclic low-density parity-check codes, IEEE Trans. Inform. Theory, 54 (2006) 71-81; doi:10.1109/TCOMM.2005.861667],

A finite incidence structure is given by a pair (P, L) where P is a finite set called the set of points and L is the set of lines, which are subsets of P of a fixed size. Classical examples may be obtained by considering P to be a set of r-dimensional subspaces of a finite dimensional vector space V over a finite field F, and L a set of s-dimensional subspaces of V, where s ≥ r + 1 . A point x e P is incident with the line I (i.e. , x ∈ I) if and only if the r-dimensional subspace x is contained in the s-dimensional subspace I. A check matrix for an LDPC code may be made from (P, L) by labelling the rows by elements x of P and the columns by elements I of L. The corresponding entry is zero if x is not in I and 1 if x ∈ I.

It is known that finite projective, affine and polar spaces may provide check matrices for LDPC codes which are quasi-cyclic. In [Y. Kou, S. Lin and M. P. C. Fossorier, "Low- density parity-check codes based on finite geometries: a rediscovery and new results,” in IEEE Transactions on Information Theory, vol. 47, no. 7, pp. 2711-2736, Nov. 2001 , doi: 10.1109/18.959255] the quasi-cyclic structure of finite projective and affine spaces are used to construct efficient LDPC codes of lengths up to approximately 16,000 bits. To construct longer codes however, they use column splitting operations. This results in codes of significantly longer length, up to approximately 500,000 bits, but these codes are not geometric, although they may perform close to Shannon’s limit, see Example 4. Meanwhile, in [Zhenyu Liu and D. A. Pados, "LDPC codes from generalized polygons,” in IEEE Transactions on Information Theory, vol. 51 , no. 11 , pp. 3890-3898, Nov. 2005, doi: 10.1109/TIT.2005.856936.] the block sizes b of the quasi-cyclic matrices for finite generalized polygons is determined. Again, however, there is no method given to actually construct these matrices for codes of arbitrarily long length such as, e.g., above approximately 20000 bits. Thus, there is, until now, no known method to calculate the check matrices of long geometric LDPC codes. Herein, it is described how this may be done by using certain equations which allow the construction of a quasi-cyclic check matrix for such codes.

An object of this disclosure is to provide new methods, systems, computer systems and computer programs aimed at improving currently known digital communication coding methods, systems, computer systems and computer programs.

SUMMARY

In an aspect, digital communication coding methods (or simply coding methods) are provided, said methods comprising providing families of quasi-cyclic low-density parity- check codes, LDPC codes, each represented by a single equation. Said single equation is derived from a geometry whose nature implies good error correcting properties for each of the LDPC codes and allows quasi-cyclic parity check matrices to be constructed for geometric LDPC codes of exceedingly long length, up to and exceeding four hundred thousand bits. The construction of such check matrices is not possible by any other known method. The LDPC codes have different lengths and different rates and the families of LDPC codes are provided with a guarantee of minimum distance. The geometric and quasi-cyclic properties of the LDPC codes allow low complexity decoding with very low frame error rates.

Digital communication coding methods may further comprise puncturing at least one check bit from one or more of the LDPC codes.

Digital communication encoding methods (or simply encoding methods) are provided. These encoding methods are described in other parts of the disclosure. The encoding is done by adding redundancy bits based on LDPC codes generated by the coding method.

Digital communication decoding methods (or simply decoding methods) are provided. These decoding methods are described in other parts of the disclosure. The decoding is done by correcting errors introduced by potentially noisy communication channel, said correction based on innovative LDPC codes generated or outputted by the coding method.

Methods of producing a digital communication coding hardware (or simply coding hardware) may be provided. Said methods include a coding method such as the ones described in other parts of the disclosure and producing the coding hardware based on innovative LDPC codes generated or outputted by the coding method. Digital communication coding hardwares generated by methods of producing coding hardware may also be provided.

In a further aspect, digital communication coding systems (or simply coding systems) are provided. These systems comprise a system module configured to provide families of quasi-cyclic low-density parity-check, LDPC, codes each represented by a single equation. Such a single equation is derived from a geometry whose nature implies good error correcting properties for each of the LDPC codes and allows quasi-cyclic parity check matrices to be constructed for geometric LDPC codes of exceedingly long length, up to and in excess of four hundred thousand bits. The construction of such check matrices is not possible by any other known method. The LDPC codes have different lengths and different rates, and the families of LDPC codes are provided with a guarantee of minimum distance. The geometric and quasi-cyclic properties of the LDPC codes allow low complexity decoding with very low frame error rates.

Digital communication transmission systems (or simply transmission systems) are disclosed. These transmission systems may include an encoding module and a transmission module. The encoding module may be configured to encode data based on innovative LDPC codes generated by any of the methods, systems, computing systems and computing programs aimed at that, which are described in other parts of the disclosure. The transmission module may be configured to transmit the encoded data through, e.g., a potentially noisy communication channel.

Digital communication receiver systems (or simply receiver systems) are disclosed. These receiver systems may comprise a receiving module and a decoding module. The receiving module may be configured to receive data through, e.g., a potentially noisy communication channel. The decoding module may be configured to decode the received data based on innovative LDPC codes generated by any of the methods, systems, computing systems and computing programs aimed at that, which are described in other parts of the present disclosure.

In a still further aspect, a computer program is provided comprising program instructions for causing a computer or computing system to perform digital communication coding methods such as the ones described in other parts of the disclosure. The computer program may be embodied on a storage medium and/or carried on a carrier signal.

In a furthermore aspect, a computing system is provided for coding data in digital communications, the computing system comprising a memory and a processor, embodying instructions stored in the memory and executable by the processor, and the instructions comprising functionality or functionalities to execute digital communication coding methods, such as the ones described in other parts of the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting examples of the disclosure will be described in the following, with reference to the appended drawings, in which:

Figure 1 is a block diagram schematically illustrating a digital communication coding system along with systems for producing digital communication coding hardware and software and combination thereof.

Figure 2 is a block diagram schematically illustrating digital communication transmission system and digital communication receiver system configured to digitally communicate with each other.

Figure 3 is a flow chart schematically illustrating a digital communication coding method along with methods of producing digital communication coding hardware and software and combination thereof, which are suitable for being performed by systems according to, e.g., Figure 1.

Figure 4 is a flow chart schematically illustrating a digital communication encoding method and a digital communication decoding method, which may be used or implemented by digital communication transmitter and receiver systems according to, e.g., Figure 2.

Figure 5 is a flow chart schematically illustrating particular manners of generating LDPC codes according to principles described with reference to Figure 1.

Figure 6 is a schematic graphic representation of the quasi-cyclic check matrix H and the quasi-cyclic generator matrix G for geometry Q(5,3).

DETAILED DESCRIPTION

Figure 1 is a block diagram schematically illustrating a digital communication coding system 100 along with systems for producing digital communication coding hardware 101 or software 102 or combination thereof 103.

As shown in this figure, digital communication coding system 100 outputs LDPC codes 105 which may then be used by system (also denominated hardware generator system) 101 to produce digital communication coding hardware, that may be configured to generate or produce corresponding digital communication coding hardware (e.g., a chip). This output of the hardware generator system 101 may be or include, e.g., a design or specs of a fully hardware-based implementation of data encoder/decoder based on innovative LDPC codes 105 outputted by digital communication coding system 100.

LDPC codes 105 outputted by digital communication coding system 100 may further or alternatively be used by system (also denominated software generator system) 102 to produce digital communication coding software, which may be configured to generate or produce corresponding digital communication coding software (or computer program). This output of the software generator system 102 may be or include a fully software- based implementation of data encoder/decoder based on innovative LDPC codes 105 from digital communication coding system 100.

LDPC codes 105 outputted by digital communication coding system 100 may further or alternatively be used by system (also denominated hardware-software generator system) 103 to produce digital communication coding hardware-software, which may be configured to generate or produce corresponding digital communication coding hardware-software. This output of the hardware-software generator system 103 may be or include an implementation of data encoder/decoder combining hardware and software based on innovative LDPC codes 105 from digital communication coding system 100.

Digital communication coding systems 100 may comprise a module (also denominated codes generator module) 104 configured to provide families of quasi-cyclic low-density parity-check, LDPC codes 105 each of which is represented by a single equation. Said single equation is derived from a geometry whose nature implies good error correcting properties for each of the LDPC codes 105. Moreover, the equations provide a quasi- cyclic check matrix for geometric LDPC codes. The lengths of these codes can be exceedingly long. Construction of such check matrices is not possible by any other known method different from digital communication coding systems 100 according to present disclosure. The LDPC codes 105 have different lengths and different rates and the families of LDPC codes 105 have a guarantee of minimum distance. The geometric and quasi-cyclic properties of the LDPC codes 105 allow the implementation of low complexity decoding with very low frame error rates. Different manners of how module 104 in digital communication coding system 100 may operate to generate corresponding LDPC codes 105 are described in detail below.

A key aspect of module 104 in digital communication coding system 100 is the generation of subsets (H ^rep ) _ij for geometric LDPC codes 105. These LDPC codes 105 have good error-correcting properties and are efficient to encode and, in turn, may be decoded quickly using low complexity decoding algorithms. The subsets (H ^rep ) _ij are predetermined by fixing a finite geometry to which an equation is associated. This equation is a low- degree polynomial f(x _j , a _j ) or f(x _i , a _j , c _j ), where x; (respectively a _j or (a _j , c _j )) runs through a determined subset of the elements of a finite field F = GF(q ^h ) representing a block of points (respectively lines) of the geometry. The block size b is a divisor of q ^h -1. Construction of the geometry in this way allows the removal of small substructures of the geometry that greatly increase the size of the blocks b, thereby enhancing the ease of implementation of the LDPC codes 105.

The LDPC codes 105 may therefore be described by their parity check matrix which may be constructed from the equation, where q may be chosen so that the LDPC code 105 has the desired rate and length. Once q and the geometry have been chosen, the block size b is given in following Tabie 1, as are the index sets of rows and columns of H ^rep . The rows are indexed by xo and the columns by a ₀ (in the projective, elliptic and symplectic case) and (a ₀ , c) (in the hermitian case), which satisfy the equation given in the final column of following Table 1. Except for the projective case, for each xo and a ₀ satisfying the defining conditions, x,, a _j e F are found such that X; ^b = xo and a _j ^b = a ₀ . In the projective case, Xi, a _j e F are found such that x ^b = xo and a? ²⁺¹ = a ₀ .

Table 1: The block size, dimension of H ^rep , finite field and the defining equation.

The rows of H ^rep are indexed by x ₀ and the columns of H ^rep are indexed by a ₀ (or (a ₀ , c)).

The conditions on a ₀ and c for H(4, q ² ) are given by (c, a ₀ ) ∈ L1 ∪ L2, where: and

The subset (H ^rep ) _ij is then determined by the defining equation in following way. Let oc be a primitive b-th root of unity in the finite field F with q ^h elements. If the defining equation is f(x _i , a _j ) (respectively f(x _i , a _j , c _j )) then the condition is r ∈ (H ^rep ) _ij if and only if (1) where r runs from 0 to b - 1 .

The reduced parity check matrix H ^rep for the dual of these codes is constructed by the rule

The length of the code, a lower bound on minimum distance, transmission rate and complexity of constructing H ^rep are given in following Table 2.

Table 2: Block size, length, and complexity of constructing H ^rep and P ^rep .

As mentioned above a quasi-cyclic generator matrix for the LDPC code 105 may be obtained efficiently by performing Gaussian elimination on the blocks of H ^rep , to obtain a quasi-cyclic parity check matrix in standard form (which may not be low-density) and then transposing the part of the matrix corresponding to the check bits in the standard way. The quasi-cyclic generator matrix may be described by a reduced generator matrix P ^rep which consists of the first row of each block matrix making up the blocks of the check bit part of the generator matrix. The matrix P ^rep may be constructed as described in [Z. Li, L. Chen, L. Zeng, W.Fong and S. Lin, "Efficient encoding of quasi-cyclic low-density parity-check codes”, IEEE Trans. Inform. Theory, 54 (2006) 71-81 ; doi:10.1109/TCOMM.2005.861667], where examples of circuits are given which implement encodings using such quasi-cyclic generator matrices. The complexity of constructing P ^rep is given in previous Table 2. A real-time field programmable gate array (FPGA) decoder was used to implement the LDPC code 105 from Q(5, 13) of length 371462. The performance of this code, as well as computer simulations for shorter length code derived from Q(5, q) (see following Table 3) consistently perform within 1-1.5dB’s of Shannon’s limit. Importantly, the LDPC codes 105 have no visible error floor. Another important advantage of using these geometric LDPC codes 105 is that low complexity decoding algorithms may be implemented which perform almost as well as slower sum-product decoding algorithms which require many iterations to converge. Such low complexity decoding algorithmsare described in [Y. Kou, S. Lin and M. P. C. Fossorier, "Low-density parity-check codes based on finite geometries: a rediscovery and new results,” h IEEE Transactions on Information Theory, vol. 47, no. 7, pp. 2711-2736, Nov. 2001 , doi: 10.1109/18.959255]. These algorithms work well partly because of a relatively high column weight. The column weights and row weights of H are detailed in previous Table 2.

Table 3: Elliptic quadric quadrangle Q(5, q).

LDPC codes 105 constructed from the point-line incidence matrices of generalised quadrangles have the property that Tanner graph of the check matrix has no cycles of length less than 8. In the case of projective and affine geometries, Tanner graph of the check matrix have no cycles of length less than 6. This, along with bounds on the minimum distance given in previous Table 2, imply good error-correcting properties.

The parameters of the LDPC codes 105 for various values of q are given in previous Table 3 and following Tables 4, 5, 6, 7 and 8. It is not necessarily the case that a quasi- cyclic generator matrix in standard form exists for all codes C, so the tables include a code C’ which is the largest subcode of C for which a quasi-cyclic generator matrix in standard form has been calculated.

Table 4: Dual elliptic quadric quadrangle Q(5, q). (t) Since the dimension of C is less than the block size a non-standard quasi cyclic generator matrix G ^rep may be obtained.

Table 5: Symplectic quadrangle W(3, q).

Table 6: Dual symplectic quadrangle W(3, q).

Table 7: Hermitian quadrangle H(4, q ² ).

Table 8: Dual Hermitian quadrangle H(4, q ² ).

Particular manners of generating LDPC codes based on above principles described regarding Figure 1 will be described later with reference to Figure 5.

Figure 2 is a block diagram schematically illustrating digital communication transmission system 200 and digital communication receiver system 208 configured to digitally communicate with each other. As shown in this figure, transmission system 200 and receiver system 208 may communicate with each other through corresponding channel 204 which may (usually) add noise to the transmission.

Transmission systems 200 may include an encoding module (or data encoder) 202 and a transmission module 203. Data encoder 202 may be configured to encode data based on innovative LDPC codes 105 generated by digital communication coding systems 100 according to the present disclosure, such as the ones described with respect to Figure 1 . Data encoder 202 may use (or include or implement) any of the methods, systems, computing systems, software, hardware and software-hardware combinations described herein that are configured to encode data (to be transmitted) based on the LDPC codes 105. Transmission module 203 may include, e.g., a modulator configured to modulate encoded data (outputted by encoding module 202) according to, e.g., specs of the channel 204 through which said encoded data is to be transmitted. Transmission systems 200 may further include, as shown in the figure, a source module 201 which may be configured to generate the data to be transmitted, pre-process preexisting data (to be transmitted) prior to its encoding (at data encoder 202), etc.

Receiver systems 208 may include a receiving module 205 and a decoding module (or data decoder) 206. Receiving module 205 may include, e.g., a demodulator configured to demodulate encoded data received through channel 204 according to, e.g., specs of the channel 204. Data decoder 206 may be configured to decode the received data (optionally once demodulated by receiving module 205) by correcting errors introduced by the (potentially) noisy communication channel 204, based on the innovative LDPC codes 105 generated by digital communication coding systems 100 according to the present disclosure, such as the ones described with respect to Figure 1. Data decoder 206 may use (or include or implement) any of the methods, systems, computing systems, software, hardware and software-hardware combinations described herein that are configured to decode data (received through channel 204) based on the LDPC codes 105. Receiver systems 208 may further include, as shown in the figure, a sink module 207 which may correspond to a destination unit where decoded data is to be processed according to intended application.

As used herein, the term “module” or “unit” may be understood to refer to software, firmware, hardware and/or various combinations thereof. It is noted that the modules are exemplary. The modules may be combined, integrated, separated, and/or duplicated to support various applications. Also, a function described herein as being performed by a particular module may be performed by one or more other modules and/or by one or more other devices instead of or in addition to the function performed by the described particular module.

The modules may be implemented across multiple devices, associated or linked to corresponding digital communication coding systems proposed herein, and/or to other components that may be local or remote to one another. Additionally, the modules may be moved from one device and added to another device, and/or may be included in both devices, associated to corresponding digital communication coding systems proposed herein. Any software implementations may be tangibly embodied in one or more storage media, such as, e.g., a memory device, a floppy disk, a compact disk (CD), a digital versatile disk (DVD), or other devices that may store computer code or computer instructions.

The digital communication coding systems according to present disclosure may be implemented by computing means, electronic means or a combination thereof. The computing means may be a set of instructions (e.g., a computer program or software) and then digital communication coding systems may comprise a memory and a processor, embodying said set of instructions stored in the memory and executable by the processor. These instructions may comprise functionality or functionalities to execute corresponding digital communication coding methods such as, e.g., the ones described with reference to other figures.

In case the digital communication coding systems are implemented only by electronic means, a controller of the system may be, for example, a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Array) or an ASIC (Application- Specific Integrated Circuit). In case the digital communication coding systems are a combination of electronic and computing means, the computing means may be a set of instructions (e.g., a computer program or software) and the electronic means may be any electronic circuit capable of implementing corresponding digital communication coding methods proposed herein, such as the ones described with reference to other figures.

The computer program(s) may be embodied on a storage medium (for example, a CD- ROM, a DVD, a USB drive, a computer memory or a read-only memory) or carried on a carrier signal (for example, on an electrical or optical carrier signal).

The computer program(s) may be in the form of source code, object code, a code intermediate source and object code such as in partially compiled form, or in any other form suitable for use in implementing digital communication coding methods according to present disclosure. The carrier may be any entity or device capable of carrying the computer program(s).

For example, the carrier may comprise a storage medium, such as a ROM, for example a CD ROM or a semiconductor ROM, or a magnetic recording medium, for example a hard disk. Further, the carrier may be a transmissible carrier such as an electrical or optical signal, which may be conveyed via electrical or optical cable or by radio or other means.

When the computer program(s) is/are embodied in a signal that may be conveyed directly by a cable or other device or means, the carrier may be constituted by such cable or other device or means. Alternatively, the carrier may be an integrated circuit in which the computer program(s) is/are embedded, the integrated circuit being adapted for performing, or for use in the performance of, digital communication coding methods proposed herein.

Figure 3 is a flow chart schematically illustrating a digital communication coding method (or simply coding method) along with methods of producing digital communication coding hardware (or simply hardware producer) and software (or simply software producer) and combination thereof (or simply hardware-software producer), which are suitable for being performed by systems according to, e.g., Figure 1. Therefore, number references from Figure 1 may be reused in following description of Figure 3.

Figure 3 thus refers to both coding methods (performed by, e.g., digital communication coding systems 100) and producer methods (performed by, e.g., digital communication coding systems 100 in cooperation with hardware generators 101 and/or software generators 102 and/or hardware-software generators 103). Full methods according to Figure 3 may also be denominated coding and producing methods herein.

As shown in the figure, coding and producing methods may be initiated (e.g., at block 300) upon detection of a starting condition such as, e.g., a user request to start the coding and producing method.

Coding and producing methods may further include (e.g., at method block 301 ) generating LDPC codes 105 in any of the innovative manners described in other parts of the disclosure. This functionality implemented or implementable by method block 301 may be performed by, e.g., codes generator module 104 (in, e.g., digital communication coding system 100) described with reference to Figure 1. Functional details and considerations explained about said codes generator module 104 (in, e.g., digital communication coding system 100) may thus be similarly attributed or attributable to method block 301.

Coding and producing methods may further include (e.g., at method block 302) verifying whether hardware (option H) or software (option S) or hardware-software (option HS) or any combination thereof (option H and/or option S and/or option HS) has or have been selected. Such an option or options (H and/or S and/or HS and/or any combination thereof) may have been provided by competent user or operator. In case of option H, transition to method block 303 may be performed. Additionally or alternatively, in case of option S, transition to method block 304 may be performed. Additionally or alternatively, in case of option HS, transition to method block 305 may be performed.

Coding and producing methods may further include (e.g., at method block 303) generating coding hardware based on innovative LDPC codes 105 (from, e.g., method block 301 ). This functionality implemented or implementable by method block 303 may be performed by, e.g., hardware generator system 101 described with reference to Figure 1 . Functional details and considerations explained about said hardware generator system 101 may thus be similarly attributed or attributable to method block 303.

Coding and producing methods may further include (e.g., at method block 304) generating coding software based on innovative LDPC codes 105 (from, e.g., method block 301 ). This functionality implemented or implementable by method block 304 may be performed by, e.g., software generator system 102 described with reference to Figure 1 . Functional details and considerations explained about said software generator system 102 may thus be similarly attributed or attributable to method block 304.

Coding and producing methods may further include (e.g., at method block 305) generating coding hardware-software based on innovative LDPC codes 105 (from, e.g., method block 301 ). This functionality implemented or implementable by method block 305 may be performed by, e.g., hardware-software generator system 103 described with reference to Figure 1. Functional details and considerations explained about said hardware-software generator system 103 may thus be similarly attributed or attributable to method block 305.

Coding and producing methods may further include (e.g., at method block 306) ending execution of the method upon satisfaction of an ending condition. Such an ending condition may be satisfied when, e.g., hardware generation has been completed (at, e.g., block 303), and/or software generation has been completed (at, e.g., block 304), and/or hardware-software generation has been completed (at, e.g., block 305), and/or user request has been detected requesting termination of the method, etc.

Figure 4 is a flow chart schematically illustrating a digital communication encoding method (or simply encoding method) and a digital communication decoding method (or simply decoding method), according to examples, which may be used or implemented by digital communication transmitter and receiver systems according to, e.g., Figure 2. Therefore, number references from Figure 2 may be reused in following description of Figure 4. In particular, encoding method 402 may be performed by encoding module 202, decoding method 405 may be performed by decoding module 206, transmission method 401 -403 may be performed by transmission system 200, and receiving method 404 - 406 may be performed by receiver system 208. Full methods exemplary illustrated by Figure 4 may be denominated transmitting and receiving methods. As shown in the figure, transmitting and receiving methods may be initiated (e.g., at block 400) upon detection of a starting condition such as, e.g., a user request to start the transmitting (and receiving) method.

Transmitting and receiving methods may further include (e.g., at method block 401 ) generating or pre-processing data to be transmitted. Block 401 may process the data in any manner that prepares the data to be encodable at block 402 and subsequently transmittable at block 403. Block 401 is not necessary if the pre-existing data does not need processing prior to its encoding at block 402. This functionality implemented or implementable by method block 401 may be performed by, e.g., source module 201 (in, e.g., digital communication transmission system 200) described with reference to Figure 2. Functional details and considerations explained about said source module 201 (in, e.g., digital communication transmission system 200) may thus be similarly attributed or attributable to method block 401 .

Transmitting and receiving methods may further include (e.g., at method block 402) encoding the data to be transmitted based on innovative LDPC codes 105. This functionality implemented or implementable by method block 402 may be performed by, e.g., encoding module 202 (in, e.g., digital communication transmission system 200) described with reference to Figure 2. Functional details and considerations explained about said encoding module 202 (in, e.g., digital communication transmission system 200) may thus be similarly attributed or attributable to method block 402.

Transmitting and receiving methods may further include (e.g., at method block 403) transmitting the encoded data through potentially noisy channel 204. This functionality implemented or implementable by method block 403 may be performed by, e.g., transmission module 203 (in, e.g., digital communication transmission system 200) described with reference to Figure 2. Functional details and considerations explained about said transmission module 203 (in, e.g., digital communication transmission system 200) may thus be similarly attributed or attributable to method block 403.

Transmitting and receiving methods may further include (e.g., at method block 404) receiving the encoded data (from transmission system 200) through a potentially noisy channel 204. This functionality implemented or implementable by method block 404 may be performed by, e.g., receiving module 205 (in, e.g., digital communication receiver system 208) described with reference to Figure 2. Functional details and considerations explained about said receiving module 205 (in, e.g., digital communication receiver system 208) may thus be similarly attributed or attributable to method block 404.

Transmitting and receiving methods may further include (e.g., at method block 405) decoding the received data based on innovative LDPC codes 105. This functionality implemented or implementable by method block 405 may be performed by, e.g., decoding module 206 (in, e.g., digital communication receiver system 208) described with reference to Figure 2. Functional details and considerations explained about said decoding module 206 (in, e.g., digital communication receiver system 208) may thus be similarly attributed or attributable to method block 405. Transmitting and receiving methods may further include (e.g., at method block 406) receiving decoded data at destination unit (in, e.g., receiver system 208). This functionality implemented or implementable by method block 406 may be performed by, e.g., sink module 207 (in, e.g., digital communication receiver system 208) described with reference to Figure 2. Functional details and considerations explained about said sink module 207 (in, e.g., digital communication receiver system 208) may thus be similarly attributed or attributable to method block 406.

Transmitting and receiving methods may further include (e.g., at method block 407) ending execution of the method upon satisfaction of an ending condition. Such an ending condition may be satisfied when, e.g., decoded data has been received at destination unit, and/or user request has been detected requesting termination of the method, etc.

Figure 5 is a flow chart schematically illustrating particular manners of generating LDPC codes according to principles described with reference to Figure 1. At method block 500, a suitable geometry is selected based on desired rate and length from Tables 3 - 8. This determines the parameters b and q and the finite field F.

Method block 501 involves running through elements of F to create the index subsets X ₀ and Ao of F given by the condition on xo and a ₀ in the last column of Table 1 .

Method block 502 involves running through elements of F to create the index subsets X and A of F where for each x ₀ ∈ X ₀ an x e F is found such that x ^b = x ₀ and for each a ₀ ∈ A ₀ an a ∈ F is found such that a ^b = a ₀ . Thus, subsets X and A of F are obtained. The size of these subsets corresponds to the number of rows (respectively columns) of H ^rep .

(if the geometry PG(3,q) is used then a is found such that

Method block 503 is the following definition: Let , where β is a primitive element of F. In this way, a is a primitive b-th root of unity in F.

Method block 504 involves the following calculation:

Method block 505 may include applying Gaussian elimination on the blocks of H ^rep , to obtain a quasi-cyclic parity check matrix in standard form (which may not be low-density) and then transposing the part of the matrix corresponding to the check bits in the standard way. The quasi-cyclic generator matrix can be described by a reduced generator matrix P ^rep which consists of the first row of each block matrix making up the blocks of the check bit part of the generator matrix.

Figure 6 is a schematic graphic representation of the quasi-cyclic check matrix H and the quasi-cyclic generator matrix G, both for geometry Q(5,3), i.e., geometry Q(5,q) with q = 3.

The block size is b = 28 and co is a primitive element of ]F ₃ 6.

For q = 3, the following is computed:

The matrix H is fully described by H ^rep , a (q + 1) x q ² matrix whose rows are indexed by elements of X and whose columns are indexed by elements of A. For x ∈ X and a ∈ A, the H _a,x entry of H ^rep is a subset of {0, whose elements indicate a 1- coordinate of the first row of the circulant matrix occupying the corresponding position in the quasi-cyclic matrix H.

Let so that a is a primitive b-th root of unity in F = F _q 6. The quasi-cyclic representation of the elliptic quadrangle is given by if and only if a(α ^r x) ^q+1 - α ^r x + a ⁹ = 0 , where r runs from 0 to b - 1.

Returning to the case q = 3, the quasi-cyclic representation of the elliptic quadrangle Q(5,3) is given by a 4 x 9 matrix H ^rep . To compute the (1,1) entry in H ^rep (i.e. the top-left entry in the matrix), those r e (0, ...,27} are determined for which a(α ^r x) ⁴ — α ^r x + a ⁹ = 0, where a = ω ² , x = ω ² and α = ω ²⁶ . It turns out that no such r exists, so is the empty set in this case. To determine the next entry in the matrix (i.e the (1,2) entry), those r e {0, ...,27} are computed for which a(α ^r x) ⁴ — α ^r x + a ⁹ = 0, where a = ω ¹⁰ , x = ω ² and a = co ²⁶ . It turns out that both r = 9 and r = 15 work, so the subset is {9,15}. Continuing in this way, it is determined that the matrix H ^rep is

To construct the quasi-cyclic check matrix H from H ^rep , we substitute each empty set with a b x b matrix of zeros and each subset {r} by an identity matrix cyclically shifted to the right by r bits. If there is more than one entry in the subset then we superimpose these cyclic shifts. Thus, the quasi-cyclic check matrix H for Q(5,3) (i.e., with q = 3) is the one shown in Figure 6 indicated with number reference 600.

Gaussian elimination is applied directly on H ^rep , to obtain a quasi-cyclic generator matrix in standard form for the code. As mentioned before, it is not always the case that there exists a generator matrix in standard quasi-cyclic form, so it is provided a generator matrix G for a large subcode C' for which there is a generator matrix in standard quasi- cyclic form. Let k be the dimension of the code C'. The matrix G can be described by a (k/b) x ((n - k)/b) matrix P ^rep , where the (i, j) entry of P ^rep is P _ij , a vector of {0,1} ^b . It is provided a matrix P ^rep , whose entries are the first row of a b x b circulant matrix. Recall that, replacing each first row with the full circulant b x b matrix, it is obtained a matrix P, where G = (P| id) is a generator matrix for the implementable code C'. In the example for q = 3 the matrix P ^rep is the following matrix:

(((0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 1 1 1 0 0 0 0 0 0 1 0 0 0) (1 0 0 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 0 0 1 0)

(1 1 1 0 1 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 0 1 1)

(1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1))

((0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0) (1 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1)

(1 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0))

((0 0 0 0 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0) (0 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0)

(0 1 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1)

(1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1))

((0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0) (1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 1 1 0 1 0)

(1 1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 1 1 1 0)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0))

((0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0) (1 0 1 1 0 0 1 1 1 1 1 1 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 1)

(1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 1 1 1 1 1)

(1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0)))

Thus, the quasi-cyclic generator matrix G for Q(5,3) (i.e. , with q = 3) is the one shown in Figure 6 indicated with number reference 601.

The block size b is 28, so the check matrix H is a 112 x 252 matrix and the generator matrix G of the code C' is a 140 x 252 matrix. This [252,140] code C' is the code whose parameters appear in the first row in Table 3. It has been constructed from the quasi- cyclic representation of the elliptic quadric quadrangle Q(5,3). Observe that is fully described by the matrices H ^rep and P ^rep .

It is understood that numerous modifications and variations could be made thereto by those skilled in the art without departing from the spirit and scope of the disclosure. For example, that labelling the rows of a parity check matrix H with r-dimensional subspaces and the columns by s-dimensional subspaces of a certain geometry, where a 1 entry is given by containment, one may deduce equations which if chosen carefully enough a quasi-cyclic matrix may be obtained. More obvious modifications may be made like removing columns blocks or row blocks. It is therefore to be understood that within the scope of the claims, the disclosure may be practiced otherwise than as specifically described herein.