Title:
RECEPTION DEVICE AND OPERATION METHOD THEREOF
Document Type and Number:
WIPO Patent Application WO/2023/054925
Kind Code:
A1
Abstract:
A reception device according to various embodiments may comprise: multiple antennas; an RF transceiver for receiving a radio frequency (RF) signal from at least one transmission device through the antennas, and processing the received RF signal into a first signal; and a processor which: generates vectors by processing the first signal; performs tree search-based detection on the basis of the generated vectors; generates, in the tree search-based detection, first candidate symbols on a first layer of a tree in a lattice reduction domain; performs a validity test for the generated first candidate symbols; and excludes a candidate symbol determined as invalid through the validity test. The processor may perform the validity test by determining whether a real number part and an imaginary number part of each of the generated first candidate symbols belong to a first real number part valid range and a first imaginary number part valid range, respectively.
Inventors:
YANG KYEONG CHEOL (KR)
YANG DAEYEOL (KR)
YANG DAEYEOL (KR)
Application Number:
PCT/KR2022/013305
Publication Date:
April 06, 2023
Filing Date:
September 06, 2022
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO LTD (KR)
POSTECH RES & BUSINESS DEV FOUND (KR)
POSTECH RES & BUSINESS DEV FOUND (KR)
International Classes:
H04B7/0413; H04B7/08; H04L1/00; H04L1/06
Domestic Patent References:
| WO2020173161A1 | 2020-09-03 |
Foreign References:
| US20180241591A1 | 2018-08-23 | |||
| US20180212737A1 | 2018-07-26 |
Other References:
ROGER SANDRA; GONZALEZ ALBERTO; ALMENAR VICENC; VIDAL ANTONIO M.: "On decreasing the complexity of Lattice-Reduction-Aided K-Best MIMO detectors", 2009 17TH EUROPEAN SIGNAL PROCESSING CONFERENCE, IEEE, 24 August 2009 (2009-08-24), pages 2411 - 2415, XP032759249, ISBN: 978-161-7388-76-7
JING-YOU LIN; JUNG-CHUN CHI; CHUN-FU LIAO; YUAN-HAO HUANG: "A 6.4G LLR/s 8×8 64-QAM soft-output MIMO detector with lattice reduction preprocessing", 2017 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), IEEE, 24 April 2017 (2017-04-24), pages 1 - 4, XP033103505, DOI: 10.1109/VLSI-DAT.2017.7939685
JING-YOU LIN; JUNG-CHUN CHI; CHUN-FU LIAO; YUAN-HAO HUANG: "A 6.4G LLR/s 8×8 64-QAM soft-output MIMO detector with lattice reduction preprocessing", 2017 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), IEEE, 24 April 2017 (2017-04-24), pages 1 - 4, XP033103505, DOI: 10.1109/VLSI-DAT.2017.7939685
Attorney, Agent or Firm:
MUHANN PATENT & LAW FIRM (KR)
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