Background of the Invention Typically in a digital signal processor (DSP), the amount of power used must be controlled to an absolute minimum.

Some existing DSP's process signals in the time domain, then in the frequency domain and subsequently in the time domain. By using two domain transitions, complex calculations and transformations need to be performed to derive output values.

Logarithmic number systems can be used for low-power operations, where multiplications between two operands can be reduced to additions of their exponents.

However, simple linear arithmetic operations such as additions and subtractions are much more complex when using the logarithmic number system.

Delta-sigma linear filtering is a suitable low-power technique because it encodes a signal and processes it with a single-bit data stream. However, delta-sigma processing requires that the original signal be oversampled which increases the complexity and power consumption of the processing system.

It is desired to provide a digital signal processing system that overcomes, or at least ameliorates some of the shortcomings of prior arrangements.

Summary According to one aspect of the invention there is provided a method for convolving a first signal and a second signal, the method comprising the steps of : resolving the first signal into a series of partial sums; resolving the second signal into a series of weighted bits and a signed bit; multiplying the first and second signals; accumulating positive output values resulting from the multiplying step; accumulating negative output values resulting from the multiplying step; and

calculating an output signal based on the accumulated positive values and the accumulated negative values.

According to another aspect of the invention there is provided a method of reducing power consumption in a signal processor, the method comprising the steps of : using multi-rate filtering to filter the spectrum of a signal input to the signal processor into multiple channels arranged in a number of octaves; time-division multiplexing the octaves over processing intervals arranged in computational sequences; band splitting and band dividing the spectrum of the signal in each octave to provide the multiple channels.

According to another aspect of the invention there is provided a system for reducing power consumption in a signal processor comprising: multi-rate filter means to filter the spectrum of a signal input to the signal processor into multiple channels arranged in a number of octaves ; time-division multiplexer means for multiplexing the octaves over processing intervals arranged in computational sequences ; the multi-rate filter means including a band splitter means for splitting each octave into a first sub-band and a second sub-band and a band divider means for dividing the first sub-band in each octave into a number of the multiple channels.

According to yet another aspect of the invention there is provided a filter comprising: resolving means for resolving the signal into a series of weighted bits and a signed bit; resolving means for resolving an impulse response into a series of partial sums; multiplying means for multiplying the series of partial sums with the series of weighted bits a signed bit; accumulating means for accumulating positive output values resulting from the multiplying step; accumulating means for accumulating negative output values resulting from the multiplying step; and

calculating means for calculating an output signal based on the accumulated positive values and the accumulated negative values.

The present invention seeks to overcome the above disadvantages by implementing a signal processing system that substantially reduces power consumption in a processor by reducing the number of operations per time through simplifying the required processing functions on an algorithmic level and simplifying the numerical operations involved in core processing. This, in turn leads to an extended battery operation of the processor due to the reduced number of recharging cycles.

Brief Description of the Drawings Preferred arrangements according to this disclosure will now be described, by way of example only, with reference to the accompanying drawings wherein: Figure 1 is a schematic diagram showing the components of an audio processor used in a cochlear implant system ; Figure 2 shows a multi-rate filter bank having five octave processing stages; Figure 3 shows a functional decomposition of an audio signal into channels processed in a time-division multiplexed format ; Figure 4 shows the decomposition of a computational interval of Figure 3, into a main processing sequence and a sub-sequence ; Figure 5 shows a sample representation of positive and negative numbers, in two's complement and sign-magnitude formats ; Figure 6 illustrates transition probabilities for multiple levels of signal correlation, represented in two's complement and sign-magnitude; and Figure 7 schematically illustrates the processing and storage of partial products resulting from a convolution process using sign-magnitude.

Detailed Description and Best Mode With reference to Figure 1 there is shown a functional block diagram of the main components of an audio processor, used for example, in a cochlear implant system. An analog audio signal is converted into digital form and then input to a DC block filter 10, to remove DC voltages in the raw audio signal. The audio signal then

input to a channel analysis filter bank 12 and decomposed into twenty analysis channels. Thus, there is one channel for each electrode in the array of electrodes in the cochlea implant.

With respect to channel #1, and this is similarly applicable to all twenty analysis channels, local functions 14 are performed. The local functions 14 include a gain modification unit 16, a peak detection and decay unit 18 for full wave rectification, and a noise floor estimation unit 20, as shown. The noise floor estimation unit 20 is the subject of a copending Australian patent application number 2003901539, which in incorporated herein by reference.

After the signal has been fully rectified, it is then input to a channel ordering unit 22 which undertakes maxima selection from the analysis channels. The channel ordering unit 22 is also the subject of an Australian copending patent application, number 2003901538, which is also incorporated herein by reference. Once the maxima are selected, these signals can be used to stimulate the auditory nerves of the cochlea implant patient.

The decomposition of the raw audio signal into the analysis channels in the channel analysis filter bank 12 is a computationally intensive task.

The channel analysis filter bank 12 in this example is a multi-rate filter bank (HRFB), which decomposes the primary spectrum X (z) of the input audio signal into sub-spectra Xi (z)... XN (z) of different bandwidth using a tree structured octave filter- bank implementation with linear phase FIR filters, as shown in Figure 2. Due to the bandwidth halving between each octave, the sampling rate can be reduced by a factor of two at each stage. This in turn can reduce the computational load in the following signal decomposition, since the individual analysis channels need only run at this reduced rate.

Thus with reference to Figure 2, there is shown the filter bank 12 comprising five octave-processing stages and four linear band divisions in each high-pass sub- band. Thus digital audio signals at 16kHz are input to a band splitter 30 in the first octave. The high pass portion of the spectrum, that is 4kHz up to 8kHz, is fed to a band divider 32 from which four channels 17 to 20 are filtered at 34 covering the spectrum from 4kHz to 8kHz. The lower half or low pass sub-band 0 to 4kHz is input to a

further band splitter 36 and the same process repeats where the high part of the signal being 2kHz to 4kHz is sent to a band divider 38 and four channels are output from the band divider being channel 13 to 16 over the range 2kHz to 4kHz. The process then repeats for the third, fourth and fifth octave whereby in the fifth octave channels one to four cover the range 250Hz up to SOOI=Iz.

At each octave level there is a rate reduction by a factor of two such that the octave processing is run at a decimated or half rate of the previous octave stage, as the bandwidth of each octave is half the bandwidth in the previous stage. Thus the rate of computation for the first octave, as only the high pass sub-band is used, is half the sampling rate. The rate of computation for the next octave, being octave 2, is one quarter of the sampling rate, for octave 3 it is one eighth of the sampling rate, for octave 4 it is one sixteenth of the sampling rate and for octave 5 it is one thirty-second of the sampling rate.

With reference to Figure 3 there is shown an example of the functional decomposition of an audio bandwidth into eighteen analysis channels. The analysis channels are chosen in such a way that, depending on the patient's residual auditory nerves, the audio bandwidth is logarithmically distributed across the available implant electrodes.

The mechanisation of the operation of an arithmetic unit has been especially chosen to match the processing requirements of the multi-rate linear filtering method.

A computational schedule is thus shown, which enables the required processing rate for each of the half-bands, and in the case of linear finite impulse response (FIR) filtering, a time domain decimation can precede the actual filtering computation.

The computational sequences required for the individual octaves, octave 1 to octave 5, are shown for the signal decomposition. The processing sequences are arranged in a time slice manner or a time division multiplexing scheme. A fundamental rule in this processing scheme is that it is implemented, as a repeating processing loop, with a length equal to two, raised to the power of the number of octaves involved in the signal decomposition.

Additionally, there is one idle processing interval for all operational cases which are indicated as X in Figure 3. Sequence 01 in a single octave system 48 repeats every

two processing intervals, the sequence 02 in the second octave 50 repeats every four processing intervals, in the third octave 52 the processing sequence 03 repeats every 8 intervals, in the fourth octave 54 the processing sequence 04 repeats every 16 processing intervals and finally in the fifth octave 56 the processing sequence 05 repeats every 32 processing intervals. During each of the processing intervals the arithmetic unit of the audio processor executes a combination of four different main sub-sequences applied to the current selected octave. The execution sequences generally vary for different octaves and depend on the configuration data as determined by the frequency allocation.

With reference to Figure 4 there is shown the decomposition of a computational (processing) interval in one of the four possible main processing sequences, for example taken from the third octave 52 shown in Figure 3. In the lower part of Figure 4, the individual sub-sequences are shown corresponding to one element of the processing interval main sequence.

The sub-sequence 60 starts with a half band splitter (HBS) sub-sequence 62 which splits the actual octave into its low and high pass portions by means of a half band FIR filter. This process generates both spectral portions through a single filtering pass by means of complementary filtering. Complementary filtering is possible when using FIR filtering, i. e., filters with linear phase response and odd filter order, and means that a single impulse response and a single convolution is used to compute two filter outputs. The first filter output is computed as an ordinary convolution of the signal and impulse response, and the second (or complementary) output is computed by flipping the sign of every other coefficient in the impulse response of the filter.

Thus, the partial products for the complementary outputs are inverted for every other sample, and accumulated to compute the complementary output. This process can be visualised as a modulation of the primary magnitude response by + 7r/2, which in <BR> <BR> the time-domain corresponds to a multiplication with a time vector: +1, -1, +1,-1, .... etc.

The high pass portion of the octave is then divided into a number of sub-bands by a band divider unit, which sub-bands are called the analysis channels, through band divider filters. Thus band divider BD1 64, band divider BD2 66 and band divider BD3

68 are all FIR filters used to separate a channel of a fixed frequency bandwidth in the high pass part of the original band. A single filtering pass generates a dual channel output through the use of complementary filtering. The channel gain and the envelope detection of each of the channels are executed in the sequence respectively via CHG 70 and PH 72 sub-sequences which follow the band dividing FIR filters. Thus for the first analysis channel the sub-sequences 70 and 72 are applied, for the second analysis channel that results from filter 66 the sub-sequences 74 to 76 are used and for a third channel that results from the filter 68 the sub-sequences 78 and 80 are respectively used for channel gain and peak hold.

The next part of this disclosure deals with an arithmetic architecture that uses sign-magnitude numbers. In most commercially available digital signal processors, two's complement is used to represent numbers in all its internal calculations at input/output data transfers. The reason for this is that the fundamental arithmetic operations of additions and subtractions are easy to perform. The two's complement system is self-correcting in the sense that no special steps are needed when operating with numbers of different sign. Both positive and negative numbers can be simply added and subtracted from one another with a result being correct in magnitude and sign at all times.

The dynamic power consumption in a digital signal processor is proportional to the number of signal transitions of all of its signal nodes per time unit. This can be represented as: P = Y2. C. V2. f Where C is the capacitance switched per operation of a type corresponding to additions, shifts, multiplication, storage and accesses, V is the operating supply voltage and f is the togging rate.

In the two's complement system, due to the duplication of the sign bit or sign extension the number of signal transitions is unfavourably large, especially when the audio signal amplitude occupies a fraction of the available dynamic range and the audio signal is uncorrelated from one sample to another.

An alternative number system is the sign-magnitude representation, in which positive and negative valued numbers are represented through the magnitude portion

and a separate sign bit. The magnitude encoding scheme is symmetrical both for positive and negative valued numbers. Shown in Figure 5 is a sample representation of positive and negative numbers in two's complement and sign magnitude. As can be seen from the two's complement representation of the numbers, the sign indicating positive values with a 0 and negative values with a 1, is part of the actual number.

There are more signal transitions also in two's complement due to the need for converting a positive magnitude into its corresponding negative magnitude by reversing the bits. For example, positive 3 is converted to negative 3 by changing 011 to 101 and indicating this with a 1 in the most significant bit position. In the sign magnitude representation the sign bit is a separate bit to the representation of the magnitude of the number and for simplicity the negative numbers have the same magnitude as their positive counterparts, for example positive 3 and minus 3 are represented by 011 and distinguished through the separate sign bit, 0 indicating positive values and 1 indicating negative values. Hence, the sign magnitude encoding scheme is symmetric for both positive and negative valued numbers.

The benefit of using the sign magnitude representation with regard to its power efficient characteristics is illustrated by Figure 6, where there is shown transition probabilities of individual bits in encoded data both for two's complement and sign- magnitude number representation. This figure is Figure 23 taken from"Minimising Power Consumption in Digital CMOS Circuits"by A. P. Chandrakasan and R. W.

Brodersen, IEEE 1995 Log Number 9408188. It shows transition probabilities for the signal nodes when represented in two's complement shown in the upper half and sign- magnitude shown in the lower half, for the case when the amplitude of the encoded signal occupies eleven bits out of sixteen possible bits. As can be seen, the transition probability in the two's complement system increases exponentially in the case that the time samples of the encoded signal are anti-correlated. The break point for the exponential growth moves towards smaller bit positions when the amplitude of the encoded signal occupies fewer bits within the numerical range of sixteen bits. As seen before, the sign-magnitude system has an advantage in terms of reduced transition probabilities and thus reduced dynamic power consumption.

However, addition and subtraction operations are difficult to perform using the sign magnitude system. More complex arithmetic is involved even though toggling in the various signal nodes is minimised.

According to this part of the disclosure, there is provided a method which can reduce the dynamic power consumption in an underlying circuit of an audio processor, for example. Specifically, multiplication operations are substituted by binary shifts and additions, and the series of shift-add-accumulates are implemented using sign- magnitude numbers and a dedicated arithmetic system.

A large number of internal computations in an audio processor involves a series of multiply-accumulate operations, which leads to a time-domain convolution of the input audio data stream, with the impulse response of the FIR filter. The following equation states the convolution as applied to digital FIR filters: M-l y (n) =Ex (n-i) h (i) i=o or in abbreviated form, y (n) = h (i) * x (n) where y (n) is the nth filter output in an M-tap FIR filter, x (n) are the various inputs of the audio signal, and h (i) is the impulse response at each value i. Thus, for example, a fourth output may be represented as: y (4) = h (0). x (4) + h (l). x (3) + h (2). x (2) + h (3). x (1) The impulse response h (i) is an array of coefficients that provides a weighted sum of the audio stream over time. Rather than calculating the multiplication of an input sample x (n) and a coefficient of the impulse response h (i), h (i) can be reduced to a series of binary shift-and accumulates, if h (i) is represented as partial sums: h (0) =Pi (0) +P2 (0) +P3 (0)...

For example if h (0) = 0.75, then : h (0) = 0. 5 +0.25 giving : PI (0) = 0. 5 = 2-1, and P2 (0) = 0.25 = 2-2 Therefore: h (0) = 2-'+ 2-2 Thus, an initial step in this optimisation process involves the simplifying the partial multiplications, x*h, to a number of power-of-two binary shifts and accumulations. The partial product of h (0). x (4) is therefore reduced to [Pl (0) + P2 (0)]. x (4).

The whole process of convolution of h (i) and x (i) is broken down into a series of partial products and then summed to produce a particular output y (n). This applies to each of the FIR filters, such as the half band splitter and band dividers previously referred to.

For example, each x value, x (0)... x (n) is represented as a sample in digital form, in sign magnitude, which is then multiplied by the impulse response at that value which can be a series of partial sums.

To obtain the eventual output y (n), various input x (n) values are multiplied by a corresponding impulse response and then a total summation made. The process then moves to its next position to be iterated to thereby obtain the next y output value.

In order to store the various positive and negative values, a system is shown in Figure 7. Input data of the audio signal, represented as x (n), is input at 100 to a barrel shifter circuit 102. Input data of the corresponding impulse response signal h (i) is input as the shift selector input 104 to the barrel shifter circuit 102.

The barrel shifter circuit 102 implements the binary shift to the input samples x (n) at the data path DATA IN (100) according to the shift amount as directed by the partial filter coefficient h (n-i) at the data path SHIFT SELECTOR (104). In order to

improve the cycle timing of the barrel shifter circuit 102, a dedicated pipeline register 105 latches the binary shifted data at the output of the barrel shifter 102.

The multiplied values at the output of the barrel shifter circuit 102 are then forwarded to a latched pipeline data register 105 and then input to both a primary data path 106 and a complementary data path 108.

In each data path, a dedicated adder 110 is used to increment the intermediate positive or negative values of the convolution and stores these in a dedicated positive data register 112 and a dedicated negative data register 114. The adder 110 receives its inputs from the latched pipeline data register 105 and selectively from the positive or negative'data registers 112,114 depending on the resulting sign of the weighting operation between the input data x (n) and filter coefficient h (n-i). This circumvents the problem of the sign-correct addition and subtractions.

A data comparator 116 compares the magnitude of the accumulated positive and negative values at the end of the convolution in a dedicated"correction step"and the corrected final result is presented to the outputs PDATAOUTPPOS and CDATAOUTPPOS. Thus a sign correct final result is calculated at the output. A saturation control block 118 ensures that the resulting data is magnitude limited and avoids numerical errors due to data truncations and growth of the internal data word length.

Thus, during the FIR filtering the positive register 112 accumulates all partial results which are positive-valued and the negative register 114 accumulates all partial results which are negative-valued. At the end of the FIR filtering or convolution, the comparator 116 checks which register has accumulated a greater magnitude so that in the following correction step the final output magnitude and sign can be generated.

As an example a three point convolution of an input stream x (n) = (-1,20, 2) with FIR filter h (n) = (-63,128,-63) would result in a first partial convolution term of (-1) * (-63) which is stored in the positive register 112 as magnitude 63. At this stage the negative register 114 is empty or equal to 0. The second partial convolution term is 20 * 128 which equals 2560 and this is added to the value 63 already stored in positive register 112. Again as both partial convolution terms are positive, the negative register

114 remains 0. For the third and final partial convolution term being 2 * (-63) = (-126) this is stored in the negative register 114 as an absolute value of 126.

Thus at the end of the convolution the comparator 116 compares the magnitudes of the two registers, with positive register 112 having a magnitude of 2623 and negative register 114 having a magnitude of 126. The comparator then flags that the positive register has a greater magnitude than the negative register by asserting the POSGETNEG flag. In the last correction step the positive register 112 subtracts from its value the number which is stored in the negative register 114 yielding a result of 2497. The sign of this number is generated to indicate that the result is positive valued. It is to be noted that for the above subtraction, the long feedback path 120 from the output of the negative register 114 to the inputs of the barrel shifter 102 is used.

Also for the above example the inverter in the feedback path is activated to negate the data which is presented at the input B of the full adder 110. This is how the above subtraction is implemented.

While the description of the preferred embodiment refers to implementation in hardware and firmware, the method can be implemented entirely in hardware, or entirely in firmware, depending on the specific application. Alternatively, the method can be implemented entirely in software, or, in a combination of software and firmware, or, a combination of software and hardware, or, a combination of software, hardware and firmware.

Moreover, the method can be encoded as a computer program on a computer readable medium, so that the computer program can be subsequently loaded or embedded into a computer system for implementation according to any one of the above arrangements.

The computer readable medium could include a CD-ROM or a floppy disk.

Other computer readable medium include magnetic tape, a ROM or integrated circuit, a magneto-optical disk, a radio or infra-red transmission channel, a computer readable card such as a PCMCIA card, and the Internet and Intrants including email transmissions and information recorded on websites and the like. The foregoing are merely exemplary of relevant computer readable mediums. Other computer readable mediums may be practiced without departing from the scope of the invention.

The preferred embodiment has been described with respect to an audio processor for a cochlear implant. However, the invention may be used in other applications such as portable communication/entertainment devices, applications involving perceptual sound encoding, speech coding for compression/encryption and video/graphics encryption and compression.

It will be appreciated by persons skilled in the art that numerous variations and/or modifications may be made to the invention as shown in the specific embodiments without departing from the scope of the invention as broadly described.

The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.