Title:
REPEATER, REPEATER CONTROL METHOD, AND COMPUTER PROGRAM
Document Type and Number:
WIPO Patent Application WO/2013/054497
Kind Code:
A1
Abstract:
The present invention achieves high-efficiency transmission for the data transmission traffic of a semiconductor system. The repeater is provided on a transmission path in an integrated circuit equipped with a distributed bus and relays data, said transmission path extending from a transmitting node to a receiving node on the distributed bus. First and second paths reaching from the repeater to the receiving node are present on the distributed bus. The repeater is equipped with a notification unit that transmits a data transfer permission request to other repeater provided on the first path and to other repeater provided on the second path and detects the presence/absence of an anomaly in the first and second paths respectively on the basis of whether or not a permission is obtained in response to the request before a predetermined waiting time expires.
Inventors:
YAMAGUCHI TAKAO
YOSHIDA ATSUSHI
ISHII TOMOKI
YOSHIDA ATSUSHI
ISHII TOMOKI
Application Number:
PCT/JP2012/006397
Publication Date:
April 18, 2013
Filing Date:
October 04, 2012
Export Citation:
Assignee:
PANASONIC CORP (JP)
International Classes:
H04L45/243; H04L12/28; H04L47/31; H04L47/30
Domestic Patent References:
| WO2010103818A1 | 2010-09-16 |
Foreign References:
| US20080084893A1 | 2008-04-10 |
Other References:
MICHIHIRO KOIBUCHI ET AL.: "A Simple Fault- tolerant Mechanism for Networks-on-Chips", IEICE TECHNICAL REPORT, vol. 107, no. 398, 12 December 2007 (2007-12-12), pages 9 - 14
Attorney, Agent or Firm:
OKUDA, SEIJI (JP)
Seiji Okuda (JP)
Seiji Okuda (JP)
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Claims: