Title:
RESISTIVE MEMORY ARRAY
Document Type and Number:
WIPO Patent Application WO/2022/111150
Kind Code:
A1
Abstract:
A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.
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Inventors:
KIM YOUNGSEOK (US)
LEE CHOONGHYUN (US)
PHILIP TIMOTHY MATHEW (US)
SEO SOON-CHEON (US)
OK INJO (US)
REZNICEK ALEXANDER (US)
LEE CHOONGHYUN (US)
PHILIP TIMOTHY MATHEW (US)
SEO SOON-CHEON (US)
OK INJO (US)
REZNICEK ALEXANDER (US)
Application Number:
PCT/CN2021/125236
Publication Date:
June 02, 2022
Filing Date:
October 21, 2021
Export Citation:
Assignee:
IBM (US)
IBM CHINA CO LTD (CN)
IBM CHINA CO LTD (CN)
International Classes:
G11C11/00
Foreign References:
| US20130201750A1 | 2013-08-08 | |||
| US20130229855A1 | 2013-09-05 | |||
| CN106448727A | 2017-02-22 | |||
| CN103378290A | 2013-10-30 | |||
| CN108346446A | 2018-07-31 |
Attorney, Agent or Firm:
CCPIT PATENT AND TRADEMARK LAW OFFICE (CN)
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