SCHEDULER, MULTI-CORE PROCESSOR SYSTEM, AND SCHEDULING METHOD

Title:

SCHEDULER, MULTI-CORE PROCESSOR SYSTEM, AND SCHEDULING METHOD

Document Type and Number:

WIPO Patent Application WO/2012/026034

Kind Code:

A1

Abstract:

A scheduler (110) preferentially places data shared by high-priority processes into memory areas having higher access speeds when parallelly executable processes assigned identical priority are executed simultaneously by CPUs, as in the multi-core processor system (100) at left. The scheduler (110) first places data shared by high-priority processes in the same manner as in the multi-core processor system (100) at left when parallelly executable processes having different levels of priority are executed simultaneously by the CPUs, as in the multi-core processor system (100) at right. The scheduler (110) then places data shared by tasks (#2, #3) having low assigned priority into the remaining memory.

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Inventors:

YAMAUCHI HIROMASA (JP)
YAMASHITA KOICHIRO (JP)
SUZUKI TAKAHISA (JP)
KURIHARA KOJI (JP)

Application Number:

PCT/JP2010/064566

Publication Date:

March 01, 2012

Filing Date:

August 27, 2010

Export Citation:

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Assignee:

FUJITSU LTD (JP)
YAMAUCHI HIROMASA (JP)
YAMASHITA KOICHIRO (JP)
SUZUKI TAKAHISA (JP)
KURIHARA KOJI (JP)

International Classes:

G06F9/48

Foreign References:

JPH07248967A	1995-09-26
JP2009509274A	2009-03-05
JPH02238556A	1990-09-20

Attorney, Agent or Firm:

SAKAI, AKINORI (JP)
Akinori Sakai (JP)

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