Title:
SELECTOR CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2005/112261
Kind Code:
A1
Abstract:
A selector circuit comprising a decode part (20) for converting a switch signal (30b) into internal control signals (20a) having the same bit width as a plurality of clock input signals (30a); and a signal selection calculating part (10), comprising a parallel connection of tri-state buffers (101) the number of which is equal to the number of bits of the plurality of clock input signals (30a) and which each receive respective one bit of the plurality of clock input signals (30a) and also each receive, as a control input, the corresponding respective one bit of internal control signal (20a) from the decode part (20), for outputting a parallel-connection output as a signal (30c) as selected. In this way, a clock signal selection can be performed by use of a simple circuit structure, so that the power consumption can be significantly reduced. Moreover, since the number of transistor stages through which the clock input signals are supplied until they are selected for output can be reduced, the time in which to select the clock input signals for output can be also significantly reduced.
Inventors:
YAMADA YUTAKA
YOSHIDA TAKESHI
YOSHIDA TAKESHI
Application Number:
PCT/JP2005/008670
Publication Date:
November 24, 2005
Filing Date:
May 12, 2005
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD (JP)
YAMADA YUTAKA
YOSHIDA TAKESHI
YAMADA YUTAKA
YOSHIDA TAKESHI
International Classes:
H03K5/00; H03K17/00; (IPC1-7): H03K17/00; H03K5/00
Foreign References:
| JPH0993283A | 1997-04-04 | |||
| JPH04319815A | 1992-11-10 | |||
| JPH06197102A | 1994-07-15 |
Attorney, Agent or Firm:
Hayase, Kenichi (13F NISSAY SHIN-OSAKA Bldg., 3-4-30, Miyahara, Yodogawa-k, Osaka-shi Osaka 03, JP)
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