Technical Field

Embodiments of the present disclosure relate to the field of semiconductor devices and processing and, in particular, self-aligned capacitors in embedded dynamic random access memory (eDRAM) one-transistor one-capacitor (1T-1C) unit cells and methods of fabricating self-aligned capacitors in eDRAM 1T-1C unit cells.

Background

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.

1T-1C unit cells may be used in the manufacture of integrated circuit devices, such as, for example, eDRAM. Scaling 1T-1C unit cells has not been without consequence. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming.

Brief Description of the Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

Fig. 1 illustrates a cross-sectional view of a self-aligned capacitor in a 1T-1C unit cell, in accordance with various embodiments.

Figs. 2A, 2B, 2C, 2D, 2E, and 2F illustrate cross-sectional views of various operations of the fabrication of a self-aligned capacitor in a 1T-1C unit cell, in accordance with various embodiments, where:

Fig. 2A illustrates a transistor as a starting structure for fabrication of a self-aligned capacitor in a 1T-1C unit cell; Fig. 2B illustrates the structure of Fig. 2A following formation of recessed electrodes;

Fig. 2C illustrates the structure of Fig. 2B following formation of an insulation layer;

Fig. 2D illustrates the structure of Fig. 2C following formation of a trench;

Fig. 2E illustrates the structure of Fig. 2D following formation of an opening; and

Fig. 2F illustrates the structure of Fig. 2E following formation of a self-aligned capacitor.

Figs. 3A, 3B, 3C, and 3D illustrate cross-sectional views of various operations of the fabrication of a self-aligned capacitor in a 1T-1C unit cell, in accordance with various embodiments, where:

Fig. 3 A illustrates the structure of Fig. 2E;

Fig. 3B illustrates the structure of Fig. 3A following formation of a first plate of a self- aligned capacitor in a 1T-1C unit cell;

Fig. 3C illustrates the structure of Fig. 3B following formation of a dielectric layer of a self-aligned capacitor in a 1T-1C unit cell; and

Fig. 3D illustrates the structure of Fig. 3C following formation of a second plate of a self- aligned capacitor in a 1T-1C unit cell.

Fig. 4 illustrates an example operation flow of fabricating a self-aligned capacitor in a 1T-1C unit cell, in accordance with various embodiments.

Fig. 5 illustrates an example electronic device, in accordance with various embodiments.

Description of the Embodiments

Self-aligned capacitors in eDRAM 1T-1C unit cells and methods of fabricating self- aligned capacitors in eDRAM 1T-1C unit cells are described. The following detailed description refers to the accompanying drawings. The same reference numbers may be used in different drawings to identify the same or similar elements. In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc., in order to provide a thorough understanding of the various aspects of the claimed embodiments. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the embodiments claimed may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well-known devices, circuits, integrated circuit design layouts, and methods are omitted or simplified so as not to obscure the description of embodiments of the present disclosure with unnecessary detail. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. For example, the thickness of substrates, layers, regions, etc., may be exaggerated for clarity. Various aspects of the illustrative embodiments may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that alternate embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations may be set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that alternate embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative

embodiments.

The phrase“in an embodiment,”“in embodiments,”“in various embodiments,”“in some embodiments,” and the like are used repeatedly. The phrase generally does not refer to the same embodiments; however, it may, and thus may refer to one or more of the same or different embodiments. The terms’’comprising,”“having,” and“including” are synonymous, unless the context dictates otherwise. The phrase“A or B” means (A), (B), or (A and B).

The following description may use certain terminology for the purpose of reference only, and thus are not intended to be limiting. For example, perspective-based descriptions such as “upper”,“lower”,“above”, and“below”, and“under” may refer to directions in the drawings to which reference is made. For another example, terms such as“front”,“back”,“top”,“bottom”, “rear”, and“side” may describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.

The term“coupled with,” along with its derivatives, may be used herein.“Coupled” may mean one or more of the following.“Coupled” may mean that two or more elements are in direct physical or electrical contact. However,“coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term“directly coupled” may mean that two or more elements are in direct contact.

It will be understood that when an element, such as, for example, a layer, region, or substrate, is referred to as being“on” another element, it may be directly on the other element or intervening elements may also be present. Further, it will be understood that when the element is referred to as being“on” another element, it may be“on” the other element regardless of whether the elements are in a vertical orientation, a horizontal orientation, or an angled orientation. Further, the phrase“a first feature formed, deposited, or otherwise disposed on a second feature,” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

Various operations may be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the illustrative embodiments; however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Further, example embodiments may be described as a process or operation flow depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram.

Although a flowchart may describe the operations as a sequential process or operation flow, many of the operations may be performed in parallel, concurrently, or simultaneously. In addition, the order of the operations may be re-arranged. A process or operation flow may be terminated when its operations are completed, but may also have additional operations not included in the figure(s). A process or operation flow may correspond to a method, a function, a procedure, a subroutine, a subprogram, and the like. When a process or operation flow corresponds to a function, its termination may correspond to a return of the function to the calling function and/or the main function.

One or more embodiments described herein are directed to approaches to fabricating self- aligned capacitors in eDRAM 1T-1C unit cells. Embodiments may include one or more self- aligned capacitors in eDRAM 1T-1C unit cells. Semiconductor devices such as eDRAM may include a plurality of unit cells, each of which may include one transistor (1T) and one capacitor (1C) that may be in series or in parallel. In eDRAM, unit cells are periodically read and refreshed. Owing to the advantages of low price-per-unit-bit, high integration, and ability to simultaneously perform read and write operations, eDRAM has enjoyed widespread use in commercial applications. Although the 1T-1C unit cells described herein may be useful for eDRAM technology, embodiments described herein need not be so limited in application.

Examples of other technology with which embodiments herein may be useful may include, but are not limited to, other types of DRAM, other types of RAM, other types of volatile memory, or other types of memory.

To provide context, one or more embodiments described herein may address the problems of capacitor shorting and transistor-capacitor misalignment in a 1T-1C unit cell. For example, with regard to capacitor shorting, a trench, which may also be referred to as a hole, may be provided for fabrication of a first capacitor, and the trench may have sides that are tapered at its open end, rather than sides that are closer to vertical and parallel. A bottom plate of the first capacitor may be fabricated at the closed end of the trench, while a top plate of the first capacitor may be fabricated at the taper open end. If, for example, an adjacent trench provided for fabrication of a second capacitor also has tapered sides at its open end, the top plate of the second capacitor may be close in proximity to the top plate of the first capacitor, especially if 1T-1C unit cells are closer in proximity as a result of scaling. The proximity of the top plates of the first and second capacitors may cause a short between them.

Further, in connection with misalignment, for example, a capacitor may need to be properly aligned with an electrode of a transistor, so that a via between a plate of the capacitor and the electrode is in the proper position to enable an electrical connection between the capacitor and the transistor. Accordingly, a trench provided for fabrication of the capacitor may be positioned over the electrode, which may be, for example, at the edge of the transistor. If the trench is not placed in the correct position, a capacitor fabricated in the trench may be misaligned relative to a via provided to connect the capacitor and the electrode, and thus the electrical connection may not be established between the transistor and capacitor. Additionally or alternatively, 1T-1C unit cell fabrication techniques that may result in capacitor shorting or transistor-capacitor misalignment may include, for example, using one mask to fabricate the transistor, a different mask to fabricate the via, and a different mask to fabricate the capacitor, where the mask used to fabricate the capacitor must be properly aligned with the via.

Embodiments described herein may include a self-aligned capacitor in a 1T-1C unit cell that may eliminate, mitigate, or reduce capacitor shorting. For example, a trench for fabricating a self-aligned capacitor in a 1T-1C unit cell may be located between electrodes of a transistor, rather than over one of the electrodes. Consequently, a top plate of a capacitor in a first 1T-1C unit cell that includes a self-aligned capacitor fabricated in the trench between two electrodes of the first 1T-1C unit cell may be less likely to be as close in proximity to the top plate of a capacitor in an adjacent second 1T-1C unit cell that includes a self-aligned capacitor fabricated in a trench between two electrodes of the second 1T-1C unit cell, which may eliminate, mitigate, or reduce capacitor shorting.

Additionally or alternatively, embodiments herein may include a self-aligned capacitor in a 1T-1C unit cell that may eliminate, mitigate, or reduce transistor-capacitor misalignment. For example, placement of the trench in accordance with various embodiments may result in elimination, mitigation, or reduction of transistor-capacitor misalignment. For example, given that the trench may be placed between two electrodes in the middle of the transistor, rather than over one electrode toward an edge of the transistor, a connection, for example, a via, between a plate of the capacitor and an electrode of the transistor may be aligned and thus in the proper position to enable a connection between the capacitor and the transistor. Additionally or alternatively, a fabrication technique for a self-aligned capacitor in a 1T-1C unit cell in accordance with various embodiments may result in elimination, mitigation, or reduction of transistor-capacitor misalignment. For example, a fabrication technique for a self-aligned capacitor in a 1T-1C unit cell may use the same mask to fabricate the capacitor and the via in the middle of the transistor. Use of the same mask to fabricate the capacitor and the via may ensure that the capacitor and the via are aligned. As a result, the capacitor may be said to be“self- aligned.”

Additionally or alternatively, a fabrication technique for a self-aligned capacitor in a 1T- 1C unit cell in accordance with various embodiments may result in a reduction in the number of masks used to fabricate a 1T-1C unit cell. For example, as noted above, the same mask may be used to fabricate the capacitor and the via, rather than using one mask to fabricate the via and a different mask to fabricate the capacitor. As a result, the number of masks used to fabricate the 1T-1C unit cell may be reduced.

Fig. 1 illustrates a cross-sectional view of a self-aligned capacitor in a 1T-1C unit cell, in accordance with various embodiments. In one embodiment, 1T-1C unit cell 100 may include a transistor 110. Transistor 110 may include a gate electrode layer 112, a gate oxide layer 114 on the gate electrode layer 112, and a thin film transistor (TFT) channel layer 116 on the gate oxide layer 114. Gate electrode layer 112 may also be referred to as a metal gate layer, gate metal layer, or an electrode layer. Gate oxide layer 114 may also be referred to as a gate dielectric layer or as a metal oxide layer. Transistor 110 may be a planar transistor, as shown in Fig. 1, or nonplanar transistor, such as a double-gate or tri-gate transistor. As used herein, reference to an element may, additionally or alternatively, be a reference to a surface of the element, or may include a reference to a surface of the element.

Transistor 110 may further include an interlayer dielectric (ILD) (not shown as a whole element) on the TFT channel layer 116. The ILD may include an ILD middle portion 118 A, which may also be referred to as a middle portion of the ILD, and one or more ILD side portions 118B. An ILD side portion may be referred to as a side portion of the ILD, and ILD side portions may be referred to as side portions of the ILD. Depending on the context, a reference to the ILD side portion may be a reference to more than one ILD side portion. Further, depending on the context, a reference to the ILD may be a reference to the ILD as a whole or a reference to, individually or collectively, the ILD middle portion 118A or the ILD side portion 118B. Further, depending on the context, a reference to the ILD middle portion 118A or the ILD side portion 118B may be, individually or collectively, a reference to the ILD. Transistor 110 may further include a first electrode 120 A in the ILD and a second electrode 120B in the ILD, where the first electrode 120A and the second electrode 120B are on the TFT channel layer 116. The first electrode 120A may be referred to as a first contact of the transistor 110, and the second electrode 120B may be referred to as a second contact of the transistor 110. The ILD middle portion 118A may be between the first electrode 120A and the second electrode 120B and may isolate the first electrode 120A from the second electrode 120B. The ILD side portion 118B may be to one side of the first electrode 120A or to one side of the second electrode 120B, and may isolate the first electrode 120A or the second electrode 120B from an electrode of an adjacent transistor or from an adjacent 1T-1C unit cell.

Transistor 110 may be a field-effect transistor (FET), as shown in Fig. 1, and thus the first electrode 120A may be a source electrode or a drain electrode, and the second electrode 120B may be a drain electrode or a source electrode. However, embodiments described herein are not limited to FETs. For example, transistor 110 may be a bipolar transistor, and thus the first electrode 120 A may be an emitter or a collector, and second electrode 120B may be a collector or an emitter, gate electrode layer 112 may be a base electrode layer, a metal base layer, or a base metal layer, or an electrode layer, and the gate oxide layer 114 may be a base dielectric layer, a base oxide layer, or a metal oxide layer.

For purposes of illustration and ease of explanation, in various embodiments, first electrode 120A is an electrode on the left, while second electrode 120B is an electrode on the right. However, an electrode on the right may be the first electrode, while an electrode of left may be the second electrode. Further, if 1T-1C unit cell 100 is at a horizontal orientation, or at an angled orientation, an electrode on the top or the bottom may be the first electrode, and an electrode on the top or bottom may be the second electrode.

1T-1C unit cell 100 may further include an insulation layer 130, on the first electrode 120A, the ILD side portion 118B, and portion of the second electrode 120B. 1T-1C unit cell 100 may further include a capacitor 160. In an embodiment, capacitor 160 may include a first plate 162 on the insulation layer 130. The insulation layer 130 may isolate the first plate 162 from the first electrode 120A and the second electrode 120B.

In an embodiment, as explained in more detail below, first plate 162 may be in a trench, and the width of the trench may be within a distance defined by an outer edge of the first electrode 120A and an outer edge of the second electrode 120B. Further, in an embodiment, the first plate 162 may be on the insulation layer 130 and the ILD middle portion 118A. Capacitor 160 may further include a dielectric layer 164 on the first plate 162, and a second plate 166 on the dielectric layer 164.

1T-1C unit cell 100 may further include a via 152 between the first plate 162 and the second electrode 120B. In an embodiment, the via 152 may be located to a side of the ILD middle portion 118A that is adjacent to the second electrode 120B. In an embodiment, the via 152 is in contact with the first plate 162 and the second electrode 120B, to couple the capacitor 160 with the transistor 110. As used herein, a reference to the via 152 providing or to provide a connection between two elements, connecting or to connect two elements, coupling or to couple an element with another element, etc., may include the via 152 providing or to provide an electrical connection between the two elements, enabling or to enable an electrical connection between the two elements, or enabling or to enable the two elements to be electrically connected. Although Fig. 1 shows via 152 in contact with the ILD middle portion 118A, the via 152 need not be in contact with the ILD middle portion 118A. In another embodiment, 1T-1C unit cell 100 may include a first plate 162 that couples capacitor 160 with transistor 110, where the first plate 162 includes an integrated via to couple the first plate 162 with the second electrode 120B.

Figs. 2A, 2B, 2C, 2D, 2E, and 2F illustrate cross-sectional views of various operations of the fabrication of a self-aligned capacitor in a 1T-1C unit cell. Referring to Fig. 2A, a transistor 110 may be formed on a TFT channel layer 116. Transistor 110 may further include gate electrode layer 112, and gate oxide layer 114 on the gate electrode layer 112, with the TFT channel layer 116 on the gate oxide layer 114. Transistor 110 may include a first electrode 120A and a second electrode 120B formed in an ILD on the TFT channel layer 116.

First electrode 120A may include an outer edge 122A, and second electrode 120B may include an outer edge 122B. Further, a distance 124 may be defined as the distance from outer edge 122A to outer edge 122B. For purposes of illustration and ease of explanation, in various embodiments, outer edge 122A is a left edge of an electrode on the left and outer edge 122B is a right edge of an electrode on the right. However, outer edge 122 A may be a right edge of an electrode on the right, and outer edge 122B may be a left edge of an electrode on the left.

Further, although a 1T-1C unit cell may be at a vertical orientation and thus described as having outer edge 122A and outer edge 122B that define width 124, a 1T-1C unit cell may be at a horizontal orientation, or at an angled orientation, and thus may have outer edge 122A as an upper edge or a lower edge, and outer edge 122B as a lower edge or an upper edge that define the width 124.

The gate electrode layer 112 may be formed of metals that may be used for a gate electrode, which may include, for example, but are not limited to, hafnium; zirconium; titanium; tantalum; aluminum; alloys of these metals; nitrides of these metals, such as, for example, but not limited to, titanium nitride and tantalum nitride; and carbides of these metals such as, for example, but not limited to, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The gate oxide layer 114 may be formed of a material such as, for example, but not limited to, silicon dioxide or a high dielectric constant (high-k) material. Examples of high-k materials that may be used to form the gate oxide layer 114 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

The TFT channel layer 116 may be, for example, but is not limited to, a crystalline semiconductor substrate formed using, for example, but not limited to, a bulk silicon substrate or a sibcon-on-insulator substructure. The TFT channel layer 116 may be formed using alternate materials, which may or may not be combined with silicon, that may include, for example, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, or other Group III-V materials. The TFT channel layer 116 may be, for example, but is not limited to, a TFT semiconductor, that may be formed using, for example, but not limited to, zinc oxide, indium oxide, indium gallium zinc oxide composite, amorphous silicon, polysilicon (which may also be referred to as

poly crystalline silicon), cobalt oxide, aluminum zinc oxide, indium zinc oxide, indium tin oxide, tin oxide, copper oxide, poly-germanium, or poly-Group III-V materials. Although a few examples of materials from which TFT channel layer 116 may be formed are described, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the embodiments described herein.

The ILD may be formed using any applicable dielectric material, such as, for example, but not limited to, low dielectric constant (low-k) dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide, carbon doped oxide, silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass, and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.

The first electrode 120A and the second electrode 120B may be formed using any applicable processes. For example, dopants such as, but not limited to, boron, aluminum, antimony, phosphorous, or arsenic may be implanted into TFT channel layer 116 to form the first electrode 120A and the second electrode 120B. As another example, TFT channel layer 116 may be etched to form recesses at the locations of the first electrode 120A and the second electrode 120B. An epitaxial deposition process may be carried out to fill the recesses with a silicon alloy such as, for example, but not limited to, silicon germanium or silicon carbide, thereby forming the first electrode 120A and the second electrode 120B. Further, the epitaxially deposited silicon alloy may be doped in situ with dopants such as, for example, but not limited to, boron, arsenic, or phosphorous. Other materials may be deposited into the recesses to form the first electrode 120A and the second electrode 120B.

Referring to Fig. 2B, the first electrode 120A may be recessed relative to an uppermost surface of the ILD, to form a first recessed region 126 A, and the second electrode 120B may be recessed relative to an uppermost surface of the ILD, to form a second recessed region 126B.

The uppermost surface of the ILD may be a top surface if, for example, 1T-1C unit cell 100 is at a vertical orientation. Further, the uppermost surface of the ILD may be a side surface or an outermost surface, if, for example, a 1T-1C unit cell is at a horizontal orientation; or an angled surface, if for example, a 1T-1C unit cell is at an angled orientation. Alternatively or additionally, the uppermost surface of the ILD may be referred to as a surface of the ILD that is a farthest distance from the TFT channel layer 116. As a result of being recessed, the upper surfaces of the first electrode 120A and the second electrode 120B do not extend to the upper surface of the ILD. In an embodiment, an etching process may be used to recess the first electrode 120A, the second electrode 120B, or both. The etching process may be wet etch, dry etch, or a combination of both. The wet etch chemical or dry etch chemical that may be used to recess the first electrode 120A and the second electrode 120B may include, for example, but is not limited to, a chemical that may be used to etch a metal, which may include, for example, but is not limited to, boron trichloride, tetrafluoromethane (which may also be referred to as carbon tetrafluoride), sulfur hexafluoride, fluoroform, or chlorine. In another embodiment, a laser may be used to recess the first electrode 120A, the second electrode 120B, or both.

Referring to Fig. 2C, recessed region 126A and recessed region 126B may be filled with an insulating material to form an insulation layer 130. The insulation layer 130 may cover the first electrode 120A and the second electrode 120B. Further, the insulation layer 130 may cover the ILD middle portion 118A and the ILD side portion 118B. The insulation layer 130 may be formed of a material such as, for example, but not limited to, silicon dioxide, an oxide material, or a high-k material. Examples of materials that may be used may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In an embodiment, the insulation layer 130 may be formed of a material (or materials) that has a different etching property than a material (or materials) of the ILD, such as, for example, the ILD middle portion 118A. For example, the insulation layer 130 may be formed of a high-k material and the material of the ILD may be a low-k material. Other materials that have different etching properties may be used for the insulation layer 130 and for the ILD. In another embodiment, the insulation layer 130 may be formed of a material (or materials) that does not have a different etching property than a material (or materials) of the ILD, such as, for example, the ILD middle portion 118 A.

In an embodiment, a surface of the insulation layer 130 may be polished, using, for example, a chemical process, a mechanical process, or a chemical-mechanical process, to remove any excess insulating material. Further, planarization may refer to the removal of material to even out irregular topography of a surface and thus make the surface flat, relatively flat, or substantially flat. The surface of the insulation layer 130 may be planarized using any chemical planarization process, any mechanical planarization process, any chemical- mechanical planarization (CMP) process, or any other process that results in a surface of the insulation layer 130 being flat, substantially flat, or relatively flat.

Referring to Fig. 2D, a portion of the ILD middle portion 118A and a portion of the insulation layer 130 may be removed, to form a trench 140. A width of the trench 140 may be within the distance 124 defined by the outer edge 122 A and the outer edge 122B. In an embodiment, the trench 140 may be formed such that a capacitor formed in the trench 140 may be centered or nearly centered on the channel length of the transistor 110. The channel length of a transistor may be defined as a distance between the closest two edges of two electrodes that are separated by a structure such as, for example, an ILD, or similarly, a closest distance from an edge of a first electrode to an edge of a second electrode that is separated from the first electrode by a structure that isolates the electrodes from each other. Alternatively or additionally, the channel length may be defined as a width of a structure that isolates a first electrode from a second electrode, where the channel length is a distance from a first edge of the isolating structure that is adjacent to the first electrode to a second edge of the isolating structure that is adjacent to the second electrode. In an embodiment, a portion of the ILD middle portion 118A and a first portion of the insulation layer 130 may be removed to a depth that retains a second portion of the insulation layer 130 on the second electrode 120B.

In an embodiment, an etching process may be used to form the trench 140. The etching process may be wet etch, dry etch, or a combination of both. The wet etch chemical or dry etch chemical that may remove a portion of the ILD and a portion of the insulation layer 130 may include, for example, but is not limited to, boron trichloride, tetrafluoromethane (which may also be referred to as carbon tetrafluoride), sulfur hexafluoride, fluoroform, or chlorine. In another embodiment, a laser may be used to form the trench 140. In an embodiment, the trench 140 may have a vertical or near-vertical profile. In another embodiment, the trench 140 may taper outward from the bottom of the trench 140 to the top of the trench 140. In yet another embodiment, the trench 140 may taper outward from the top of the trench 140 to the bottom of the trench 140. Referring to Fig. 2E, a portion of the insulation layer 130 may be removed from a side of the ILD middle portion 118A that is adjacent to the second electrode 120B, to form a via opening 150 that exposes the second electrode 120B. In an embodiment, the via opening 150 may expose a portion of the second electrode 150 or a portion of the surface of the second electrode 120B. In another embodiment, the via opening 150 may expose the entire second electrode 150 or the entire surface of second electrode 120B.

In an embodiment, an etching process may be used to form the via opening 150. The etching process may be wet etch, dry etch, or a combination of both. Further, the etching process used to form the via opening 150 may be selective. That the etching process is selective may mean, for example, that the wet or dry etch chemistry may etch or otherwise remove a portion of the insulation layer 130 without etching or otherwise removing a substantial portion of the ILD middle portion 118 A. Additionally or alternatively, that the etching process is selective may mean that the wet or dry etch chemistry may etch or otherwise remove the material of the insulation layer 130 but may selectively stop and not etch the ILD middle portion 118A, or may etch or otherwise remove a small, relative to the portion of the insulation layer 130 that is etched or otherwise removed, portion of the ILD middle portion 118 A. This may, for example, align the via opening 150 with the second electrode 120B. The wet etch chemical or dry etch chemical that may differentiate between the insulating material of the insulation layer 130 and the ILD middle portion 118A may include, for example, but is not limited to, boron trichloride, sulfur hexafluoride, other fluorine-based or other chlorine-based chemistries. In another embodiment, a laser may be used to form the via opening 150. In an embodiment, the wet etch or dry etch chemical itself may etch or otherwise remove the insulating material of the insulation layer 130. In another embodiment, the wet etch or dry etch chemical may make the insulating material of the insulation layer 130 more susceptible to being etched or otherwise removed.

Referring to Fig. 2F, capacitor 160 may be formed in the trench 140, where the capacitor 160 is coupled with the transistor 110. The capacitor 160 may include first plate 162, dielectric layer 164 on the first plate 162, and second plate 166 on the dielectric layer 166. The capacitor 160 may be any type of capacitor, such as, for example, but not limited to, a metal-insulator- metal (MIM) capacitor.

In an embodiment, a conductive material in the via opening 150 may form a via 152 between the first plate 162 of the capacitor 160 and the second electrode 120B of the transistor 110. The via 152 may couple the first plate 162 with the second electrode 120B, to couple the capacitor 160 with the transistor 110. The conductive material in the via opening 150 may be any conductive material, such as, for example, but not limited to, aluminum, tantalum, silver, copper, tungsten, nickel, cobalt, or other metals, or may be an alloy, such as, for example, but not limited to, a metal-metal alloy or a metal-semiconductor alloy, such as, for example, but not limited to, a silicide material. The conductive material in the via opening 150 may couple the first plate 162 with the second electrode 120B without regard to whether the conductive material in the via opening 150 forms a via 152. In an embodiment, the via 152 may be formed separately from the first plate 162. In another embodiment, the via 152 may be integrated with the first plate 162. In an embodiment, the first plate 162 and the via 152 may be made of the same conductive material. In another embodiment, the first plate 162 may be made of a first conductive material, and the via 152 may be made of a second, different conductive material.

Figs. 3A, 3B, 3C, and 3D illustrate cross-sectional views of various operations of the fabrication of a self-aligned capacitor in a 1T-1C unit cell, in accordance with various embodiments. Referring to Fig. 3A, the structure of Fig. 2E is provided. Referring to Fig. 3B, the via opening 150 and the trench 140 may be filled with a conductive material, to form a first plate 162 of a capacitor 160. In an embodiment, the conductive material in the via opening 150 may couple the first plate 162 with the surface of the second electrode 120B. Further, the first plate 162 may cover the insulation layer 130 and the ILD. The first plate 162 may be made of any conductive material, such as, for example, but not limited to, aluminum, tantalum, silver, copper, tungsten, nickel, cobalt, or other metals, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

Referring to Fig. 3C, a dielectric layer 164 of capacitor 160 may be formed on the first plate 162. The dielectric layer 164 may be made of any applicable dielectric material, such as, for example, but not limited to, silicon dioxide, silicon nitride, or a high-k material, such as, for example, but not limited to, silicon oxy -nitride, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy -nitride, titanium oxide, or lanthanum oxide.

Referring to Fig. 3D, a second plate 166 of capacitor 160 may be formed on the dielectric layer 164. In an embodiment, the second plate 166 may be made of any conductive material, such as, for example, but not limited to, aluminum, tantalum, silver, copper, tungsten, nickel, cobalt, or other metals, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

Fig. 4 illustrates another example operation flow of fabricating a self-aligned capacitor in a 1T-1C unit cell, in accordance with various embodiments. Operation flow 400 may include, at 402, forming, in an ILD on a TFT channel layer, a first electrode of a transistor and a second electrode of the transistor. In an embodiment, operation flow 400 may further include forming a gate oxide layer, where the TFT channel layer is on the gate oxide layer, and forming a gate electrode layer, wherein the gate oxide layer is on the gate electrode layer.

Operation flow 400 may further include, at 404, recessing, relative to an uppermost surface of the ILD, the first electrode, to form a first recessed region, and the second electrode, to form a second recessed region. In an embodiment, recessing, relative to the uppermost surface of the ILD, the first electrode, to form the first recessed region, and the second electrode, to form the second recessed region, may include etching the first electrode and the second electrode. Operation flow 400 may further include, at 406, filling with an insulating material, to form an insulation layer, the first recessed region and the second recessed region, where the insulating material covers the first electrode, the second electrode, and an ILD side portion. In an embodiment, operation flow 400 may include polishing the insulation layer.

Operation flow 400 may further include, at 408, removing, to form a trench, a portion of an ILD middle portion between the first electrode and the second electrode and a portion of the insulation layer, where a width of the trench is within a distance defined by an outer edge of the first electrode and an outer edge of the second electrode. In an embodiment, removing, to form the trench, the portion of the ILD middle portion and the portion of the insulation layer, may include removing, to form the trench, the portion of the ILD middle portion and a first portion of the insulation layer to a depth that retains a second portion of the insulation layer material on the second electrode.

Operation flow 400 may further include, at 410, removing, to form a via opening, a portion of the insulation layer that is to a side of the ILD middle portion, where the side of the ILD middle portion is adjacent to the second electrode, and where the via opening exposes a portion of the second electrode. In an embodiment removing, to form the via opening, the portion of the insulation layer that is to a side of the ILD middle portion that is adjacent to the second electrode may include etching the portion of the insulation layer that is to the side of the ILD middle portion that is adjacent to the second electrode.

Operation flow 400 may further include, at 412, filling the via opening with a conductive material, to form a via, where the via is in contact with the second electrode. Operation flow 400 may further include, at 414, filling the trench with the conductive material, to form a first plate of a capacitor, where the first plate is in contact with the via, and where the via couples the first plate with the second electrode. Operation flow 400 may further include, at 416, forming, on the first plate, a dielectric layer of the capacitor. Operation flow 400 may further include, at 418, forming, on the dielectric layer, a second plate of the capacitor.

In an embodiment, operation flow 400 may further include removing, to form an opening, a portion of the insulation layer that is to a side of the ILD middle portion, where the side of the ILD middle portion is adjacent to the second electrode and where the opening exposes a portion of the second electrode, and filling the opening and the trench with a conductive material, to form a plate of a capacitor, where the conductive metal in the opening couples the plate with the second electrode. In an embodiment, the conductive material in the opening may form a via.

Fig. 5 illustrates an example electronic device, in accordance with various embodiments. The computing device 500 houses a board 502. The board 502 may include a number of components, including but not limited to a processor 504 and at least one communication chip 506. The processor 504 is physically and electrically coupled to the board 502. In some implementations the at least one communication chip 506 is also physically and electrically coupled to the board 502. In further implementations, the communication chip 506 is part of the processor 504.

Depending on its applications, computing device 500 may include other components that may or may not be physically and electrically coupled to the board 502. These other components include, but are not limited to, volatile memory, e.g., DRAM or eDRAM, such as, for example, eDRAM 508, that may include a self-aligned capacitor in a 1T-1C unit cell, e.g., 1T-1C unit cell 100, as described in accordance with embodiments herein, non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 506 enables wireless communications for the transfer of data to and from the computing device 500. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 506 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 500 may include a plurality of communication chips 506. For instance, a first communication chip 506 may be dedicated to shorter range wireless

communications such as Wi-Fi and Bluetooth and a second communication chip 506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 504 of the computing device 500 includes an integrated circuit die packaged within the processor 504. In some implementations of embodiments of the present disclosure, the integrated circuit die of the processor includes one or more devices, such as metal oxide semiconductor field effect transistors (MOS-FETs) built in accordance with

implementations of the embodiments. The term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 506 also includes an integrated circuit die packaged within the communication chip 506. In accordance with another implementation of embodiments of the present disclosure, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FETs built in accordance with implementations of the embodiments. In further implementations, another component housed within the computing device 500 may contain an integrated circuit die that includes one or more devices, such as MOS-FETs built in accordance with implementations of embodiments of the present disclosure.

In various embodiments, the computing device 500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 500 may be any other electronic device that processes data.

Thus, embodiments herein include self-aligned capacitors in eDRAM 1T-1C unit cells and methods of fabricating self-aligned capacitors in eDRAM 1T-1C unit cells.

Some non-limiting examples are provided below.

Examples

Example 1 may include a semiconductor device unit cell, comprising: a transistor, wherein the transistor includes: a thin film transistor (TFT) channel layer; an interlayer dielectric (ILD) on the TFT channel layer, wherein the ILD includes an ILD middle portion and an ILD side portion; a first electrode in the ILD and a second electrode in the ILD, wherein the first electrode and the second electrode are on the TFT channel layer, and wherein the ILD middle portion is between the first electrode and the second electrode; a capacitor, wherein the capacitor includes a plate in a trench, and wherein a width of the trench is within a distance defined by an outer edge of the first electrode and an outer edge of the second electrode; and a via, to couple the capacitor with the transistor, wherein the via is in contact with the plate and the second electrode, and wherein the via is located to a side of the ILD middle portion that is adjacent to the second electrode.

Example 2 may include the semiconductor device of Example 1 or some other example herein, wherein the transistor further comprises: a gate oxide layer, wherein the TFT channel layer is on the gate oxide layer; and a gate electrode layer, wherein the gate oxide layer is on the gate electrode layer.

Example 3 may include the semiconductor device of Example 1 or 2 or some other example herein, further comprising an insulation layer on the first electrode, an ILD side portion, and a portion of the second electrode.

Example 4 may include the semiconductor device of Example 3 or some other example herein, wherein the first plate is on the insulation layer and the ILD middle portion.

Example 5 may include the semiconductor device of Example 2 or some other example herein, wherein the insulation layer comprises an insulating material that has a different etching property than a material of the ILD.

Example 6 may include the semiconductor device of Examples 1, 2, 4, or 5 or some other example herein, wherein the insulating material comprises a high dielectric constant material and the material of the ILD comprises a low dielectric constant material.

Example 7 may include the semiconductor device of Example 1, 2, 4, or 5 or some other example herein, wherein the plate is a first plate, and wherein the capacitor further comprises: a dielectric layer on the first plate; and a second plate on the dielectric layer.

Example 8 may include an embedded dynamic random access memory (eDRAM), comprising: a transistor, wherein the transistor includes: a thin film transistor (TFT) channel layer; an interlayer dielectric (ILD) on the TFT channel layer; a first electrode in the ILD and a second electrode in the ILD, wherein the first electrode and the second electrode are on the TFT channel layer, and wherein the ILD middle portion is between the first electrode and the second electrode; an insulation layer, wherein the insulation layer is on the first electrode, an ILD side portion, and a portion of the second electrode; a capacitor on the insulation layer, wherein the capacitor includes: a first plate in a trench, wherein a width of the trench is within a distance defined by an outer edge of the first electrode and an outer edge of the second electrode, and wherein the first plate is on the insulation layer and the ILD middle portion; a dielectric layer on the first plate; and a second plate on the dielectric layer; and a via, to couple the capacitor with the transistor, wherein the via is between the first plate and the second electrode, and wherein the via is in contact with the first plate and the second electrode.

Example 9 may include the eDRAM of Example 8 or some other example herein, wherein the transistor further comprises: a gate oxide layer, wherein the TFT channel layer is on the gate oxide layer; and a gate electrode layer, wherein the gate oxide layer is on the gate electrode layer.

Example 10 may include the eDRAM of Example 8 or 9 or some other example herein, wherein the insulation layer comprises an insulating material that has a different etching property than a material of the ILD.

Example 11 may include the eDRAM of Example 10 or some other example herein, wherein the insulating material comprises a high dielectric constant material and the material of the ILD comprises a low dielectric constant material.

Example 12 may include a board, comprising: a memory, wherein the memory includes: a transistor, wherein the transistor includes: a thin film transistor (TFT) channel layer; an interlayer dielectric (ILD) on the TFT channel layer, wherein the ILD includes an ILD middle portion and an ILD side portion; a first electrode in the ILD and a second electrode in the ILD, wherein the first electrode and the second electrode are on the TFT channel layer, and wherein the ILD middle portion is between the first electrode and the second electrode; a capacitor, wherein the capacitor includes: a capacitor on the insulation layer, wherein the capacitor includes: a first plate in a trench, wherein a width of the trench is within a distance defined by an outer edge of the first electrode and an outer edge of the second electrode; a dielectric layer on the first plate; and a second plate on the dielectric layer; and a via, to couple the capacitor with the transistor, wherein the via is in contact with the first plate and the second electrode, and wherein the via is located to a side of the ILD middle portion that is adjacent to the second electrode; and a processor coupled with the memory.

Example 13 may include the board of Example 12 or some other example herein, wherein the memory comprises an embedded dynamic random access memory (eDRAM).

Example 14 may include the board of Example 12 or 13 or some other example herein, wherein the transistor further comprises: a gate oxide layer, wherein the TFT channel layer is on the gate oxide layer; and a gate electrode layer, wherein the gate oxide layer is on the gate electrode layer.

Example 15 may include the board of Example 12 or 13 or some other example herein, further comprising an insulation layer on the first electrode, an ILD side portion, and a portion of the second electrode.

Example 16 may include the board of Example 15 or some other example herein, wherein the first plate is on the insulation layer and the ILD middle portion.

Example 17 may include the board of Example 16 or some other example herein, wherein the insulation layer comprises an insulating material that has a different etching property than a material of the ILD.

Example 18 may include the board of Example 17 or some other example herein, wherein the insulating material comprises a high dielectric constant material and the material of the ILD comprises a low dielectric constant material. Example 19 may include a method of fabricating a semiconductor device, the method comprising: forming, in an interlayer dielectric (ILD) on a thin film transistor (TFT) channel layer, a first electrode of a transistor and a second electrode of the transistor; recessing, relative to an uppermost surface of the ILD, the first electrode, to form a first recessed region, and the second electrode, to form a second recessed region; filling with an insulating material, to form an insulation layer, the first recessed region and the second recessed region, wherein the insulating material covers the first electrode, the second electrode, and an ILD side portion; removing, to form a trench, a portion of an ILD middle portion between the first electrode and the second electrode and a portion of the insulation layer, wherein a width of the trench is within a distance defined by an outer edge of the first electrode and an outer edge of the second electrode;

removing, to form a via opening, a portion of the insulation layer that is to a side of the ILD middle portion, wherein the side of the ILD middle portion is adjacent to the second electrode, and wherein the via opening exposes a portion of the second electrode; filling the via opening with a conductive material, to form a via, wherein the via is in contact with the second electrode; filling the trench with the conductive material, to form a first plate of a capacitor, wherein the first plate is in contact with the via, and wherein the via couples the first plate with the second electrode; forming, on the first plate, a dielectric layer of the capacitor; and forming, on the dielectric layer, a second plate of the capacitor.

Example 20 may include the method of Example 19 or some other example herein, further comprising: forming a gate oxide layer, wherein the TFT channel layer is on the gate oxide layer; and forming a gate electrode layer, wherein the gate oxide layer is on the gate electrode layer.

Example 21 may include the method of Example 19 or 20 some other example herein, wherein recessing, relative to the uppermost surface of the ILD, the first electrode, to form the first recessed region, and the second electrode, to form the second recessed region, comprises etching the first electrode and the second electrode.

Example 22 may include the method of Example 19 or 20 or some other example herein, further comprising polishing the insulation layer.

Example 23 may include the method of Example 19 or 20 or some other example herein, wherein removing, to form the trench, the portion of the ILD middle portion and the portion of the insulation layer, wherein the width of the trench is within the distance defined by the outer edge of the first electrode and the outer edge of the second electrode, comprises removing, to form the trench, the portion of the ILD middle portion and a first portion of the insulation layer to a depth that retains a second portion of the insulation layer material on the second electrode, wherein the width of the trench is within the distance defined by the outer edge of the first electrode and the outer edge of the second electrode.

Example 24 may include the method of Example 19 or 20 or some other example herein, wherein removing, to form the via opening, the portion of the insulation layer that is to the side of the ILD middle portion that is adjacent to the second electrode, and wherein the via opening exposes the portion of the second electrode, comprises etching the portion of the insulation layer that is to the side of the ILD middle portion that is adjacent to the second electrode.

Example 25 may include the method of Example 24 or some other example herein, wherein etching the portion of the insulation layer that is to the side of the ILD middle portion that is adjacent to the second electrode comprises etching the portion of the insulation layer that is to the side of the ILD middle portion without etching a substantial portion of the ILD middle portion.

Various embodiments may include any suitable combination of the above-described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the“and” may be“and/or”). Furthermore, some

embodiments may include one or more articles of manufacture (e.g., non-transitory computer- readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above- described embodiments.

The above description of illustrated implementations, including what is described in the

Abstract, is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the present disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim

interpretation.